RISC-V instruction set architecture (ISA) is designed to support computer architecture research and education, and completely free for academia and industry use. By using the reference of RISCV-Angel, which is running with the RV64 (64-bit) architecture. My task is to make sure that the RISCV-Angel is able to run on the Read more…
Now for real, the circuit is finished, and I have started with assigning and creating the footprints for the components. There are no one major updates this week, but rather a lot of changes and modifications to the schematics. As usual, here is the visual diff for this week. Additions Read more…
This week I started to integrate everything together starting from the generation of the C++ code by the user up to the creation of the final bit stream. It’s the time to get every part of the project work side by side with each other. Verilog top module and EMACS: Read more…