For my second week, I couldn’t work as much as I imagined. After finishing the basic utilities and a general understanding of what I needed, I set off to write the opcodes. The opcodes require more time and effort because ultimately I would like to get it right the first time. However, that requires a general understanding of the aeMB processor.
So the key thing is that aeMB is different from MicroBlaze architecture as it allows concurrency, which means that it has another sets of general purpose registers that would handle the second thread. However, since for the current task for the simulator is to finish up the opcodes and structure, I decided to focus on just one thread and finishing up the opcodes. I estimate about two weeks for me to finish this and then I will proceed to the other structure designs.
The opcodes generally have two types: type A and type B. The two types has the format as below:
Type A
[0 – 5] [6 – 10] [11 – 15] [16 – 20] [21 – 31]
[Opcodes] [Rd] [Ra] [Rb] [11 bit number]
Type B
[0 – 5] [6 – 10] [11 – 15] [16 – 31]
[Opcodes] [Rd] [Ra] [Imm]
However, for efficiency, I decided to split them up into more detailed groups according to their instruction sets. I end up having 15 sub types, which I use a switch function to loop around for both. By the looks of it, this might be even faster than spliting into just two types. However, further testing is needed to ensure the correctness and tight complexity of this organization.
I also noticed that I will definitely need some more functions specifically for dealing with decoding the instructions and handling read and writes. I have made a small unofficial list for it, and I will be adding them in during the process.
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