With the footprints done, wrestling with PCB design continues as usual with component placement and routing. Also this week, I hit a minor snag with regards to simple yet confusing aspect of my task.
Blow-by-blow account below, but click here to leap to the summary.
Layout & Design Rules
As mentioned last week, the end-product will fit the Arduino form factor. The initial schematic had 54 digital I/O pins, but during the laying out of parts on the board a few I/O headers had to be sacrificed to make space.
The board will have a conventional 4-layer design: Layer 1 will be for signals & most components and Layer 4 will be for signals & passive components; Layers 2 and 3 will be power and ground planes respectively. There are also different power nets on Layer 2, since there will be three separate voltages used for VCCO (+3.3V), VCCAUX (+2.5V) and VCCINT (+1.2V).
When setting design rules for the board, the main factors considered include functionality, cost and space. Some traces need to be short for crucial components such as capacitors and oscillators, while differential pairs need to be kept close together and length-matched. This can quickly cause a tangle of tracks on the PCB, so the order of priority for routing is power pins > clocks & oscillators > programming lines > diff pairs > everything else.
Blind/buried vias and microvias were considered for the design, but to lower costs an attempt will be made to keep all vias through-hole, 30 thou diameter. Signal trace width is 10 thou while power trace is 25 thou, which is admittedly quite narrow but necessary to fit everything. These values will be testing the limits of the manufacturer’s PCB capabilities.
There are many other considerations to make regarding PCB design, but Xilinx has compiled a helpful checklist for FPGA development boards.
Decoupling Capacitors
For both the PIC18 and Spartan-6, decoupling capacitors are required to ensure a stable power supply to the active devices – providing a local source of charge when there is a spike in current drawn by the devices.
The placement and routing of these capacitors is a deceptively simple task. One might be tempted to simply wire the capacitors to the supply and ground pins of the devices, but careless design will render the capacitors completely useless! The main goal in capacitor placement is to minimise the AC impedance of the supply rails. Geometry is crucial, since long traces to the pads not only contributes to greater resistance but more significantly greater inductance at high frequencies; the inductance is proportional to the size of the loop for current flowing through the capacitor.
Hence, it is best to have the decoupling capacitors as close as possible to the voltage pins with wide and short traces. For this reason (and also to conserve board area), the decoupling capacitors are positioned on the bottom of the PIC18 and Spartan-6 devices, mostly within their footprints. Vias are used to connect the capacitors to the power & ground planes directly. The vias should be butting directly against the SMD capacitor pads, and no two capacitors should share vias since this will throttle current flow and increase spreading inductance. The placement of vias on the sides of pads will further lessen the size of the current loop and thus inductance.
One difficulty encountered in this work is that there are no standard rules of thumb regarding decoupling capacitors in PCB designs, and sometimes conflicting advice on this matter is given online. However, the main reference text used are recommendations for capacitor selection and placement in the Spartan-6 FPGA PCB Design and Pin Planning Guide (p14, UG393) and the PIC18F97J60 Family Datasheet (p43), as well as advice on the Xilinx forums.
So the placement of components on the board is somewhat completed and probably won’t be shifted around much. Meanwhile, decoupling capacitors was the most vexing of issues faced this week, given the lack of matching examples available and my own inexperience. As such, I had to go back to the drawing board a few times with the capacitor design throughout this week.
Time is running out as the deadline approaches, and hopefully the next few stages of routing will be easier with the auto-router coming into play.
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