Dear diary,
This was my 9th week at Aeste and 2nd working on ECDSA. I am surprised but there actually is some progress in my current project. Field arithmetic part (most important) is almost done so starting from next week I can proceed to implement actual algorithm, which is not that hard after all, but requires operating on big, non-standard size variables.
As I progress with my work, I start to experience a problem that I didn’t have to worry about previously. Namely: limited resources. Of course, in my previous projects I tried my best to minimize the usage whenever and wherever I could just as a good practice (because that’s what good engineers do and I aim to be one! š ), but they were not even half as demanding as this one. Another reason why I didn’t have to worry earlier is that I was working with quite powerful Zedboard from Digilent, equipped with roughly 10 times bigger FPGA than the one company plans to use for the final product.
Hopefully in my next entry I will be able to share some more technical details and nice screenshots.
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