After second week I can say I start to know what is really going on. First of all, the language I am using is called Verilog, not Very Log as I was convinced previously. Secondly it is not required for the code to rhyme, nor each line to have equal number of syllables. Finally, dialogues are not a legit way of communication between modules.
Week’s 0010 assignment was to write a wishbone master module that is a part of a bigger project. Basically it will communicate with SPI modules of my colleagues and use them to exchange data. Our team is doing great, next month we will be probably able to start simulations (to our mentor’s delight).
Windows remains mystery to me, why is the exit cross button always on the left side?!
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