ASH1 is growing and the design is being modified continuously to allow for further flexibility and capability in performing I/O operations. However, these modifications won’t be drastic. ASH1 core is there ! So in the future, there will be slight changes in the instruction set or components. The design flow Read more…
ASH1 communicates externally with two kinds of components, a master controller (master CPU) and a typical PHY interface unit that couples ASH1 with peripherals. The communication is achieved through the following signals: Interfacing with Signal Width Direction/ Type (with respect to ASH1) Master CPU clk 1 i reset 1 Read more…
As I have mentioned in the previous post, this and the coming posts would describe ASH1 architecture and special features. Below is the block diagram of ASH1. It consists of a data stack, a control unit, a program counter, an arithmetic/ logic unit (ALU), a cyclic redundancy checksum (CRC) Read more…
One of ASH1 features is that it can perform – what we can call – software-controlled CRC calculation. As we know CRC incorporates bit shifting, xoring and in sometimes inversion. We decided to have a unit in ASH1 that is dedicated to all these operations. For instance, we want to Read more…