Finalizing I2C continues. Finally the master is fully functioning but tested only through simulation. Here is the Features of the master: Clock Synchronization and Arbitration. Detection of a busy bus. Supports Arbitration loss. Handles Slave induced waits. Capable of repeated start and back to back reads and writes. Future Improvements: Read more…
This week was very interesting and yet tiring one! I wrote my networking c++ program and began to understand how machine interacts with each other. That involved too much researching and reading. and most of the time I ended up closed lines. I spent the first few days on researching Read more…
Following the disaster of having the 4gb Kingston SD card stop responding, the focus of the week was to find a way to get the non-responsive SD cards to work on the PICTail. A lot of knowledge was gained about the SD cards initialization process (the process at which some Read more…
By the end of this month, I should be able to integrate everyone’s project in to mine, and manage them to produce the desired output I started with Verilog synthesizer.In this process, I’m supposed to execute a shell script that takes a .v file and runs on it three software Read more…
Last week I created a script to run all Xilinx tools required for implementation from the command line. We are using the 14.4 version of Xilinx software. Before using any of the tools in this version a Xilinx script is required to be executed to set required environment variables. However Read more…
This week was a real eye opener in many ways. Physically I was unwell, and mentally I was fatigued. But it throughout the week, I picked up a lot of advice from the supervisor and I hope I was able to implement some of them in my work this week. Read more…
this week was a very frustrating one, full of mysteries and brain teasers… I spent the first few days trying to get the compiler to compile some error code,and get the error message . The challenge was without using shell commands. This lasted for a day or more before I Read more…
The goal of this month is to get everything in the project working starting with the code the user is going to enter until the final bit stream that can be downloaded to the FPGA. This week has been quite productive. First of all the SOC is complete. I have Read more…
Much of the week was spent trying to find out as much as possible about the Xilinx bitstream file formats (.bit). The actual configuration within a bitstream file is encrypted and is not available for public use. The FPGA usually contains the encryption key to be able to run the Read more…
After tuns and tuns of reading, my supervisor gave me the green light to start working on my part , the web Interface. in this week, My main task was to implement the Ace editore using C++ webtool kit into the editor web page . With the help of webtool Read more…