This week I’ve fully completed I2C master and slave and tested them by simulation. Having been over that I’ve moved to learning C++ object oriented programming to write the code that creates the system top level code. There isn’t much to say about C++ so I’ll use this blog post Read more…
Finalizing I2C continues. Finally the master is fully functioning but tested only through simulation. Here is the Features of the master: Clock Synchronization and Arbitration. Detection of a busy bus. Supports Arbitration loss. Handles Slave induced waits. Capable of repeated start and back to back reads and writes. Future Improvements: Read more…
The I2C core made a lot of progress this week. While I was hoping last week not to use a FSM in my slave I couldn’t resist the temptation. My slave have a FSM and is almost 95% ready. The hardest part is the acknowledge part. Not only that the Read more…
I2C is the last IO device going into our system, for now. I2C is more complicated than both UART and SPI. It’s complication is due to it’s ability to have many masters and slaves on the same bus. Moreover, having only one bidirectional line(SDA) for data transfer adds to it’s Read more…