Engineering Elegance

Shooting Troubles #1

As a part of my training I was to play a little bit with the Zedboard development kit from Digilent. Unfortunately, running all of the provided by Xilinx tools (ISE 14.4) on linux (Ubuntu 12.04 LTS here) can be sometimes problematic. I will try to list all the issues I encountered while going through these tutorials http://www.zedboard.org/course/introduction-zynq as well as their solutions. Proposed solutions are not something new, I didn’t came up with them, this series of posts serves only Read more

By radoslawk, ago

Week 0010

After second week I can say I start to know what is really going on. First of all, the language I am using is called Verilog, not Very Log as I was convinced previously. Secondly it is not required for the code to rhyme, nor each line to have equal number of syllables. Finally, dialogues are not a legit way of communication between modules. Week’s 0010 assignment was to write a wishbone master module that is a part of a Read more

By radoslawk, ago

SPI Slave Modifications

In my fourth week at AESTE, I worked on my spi design. I made many many changes with the help of my mentor. Firstly, I was able to introduce an edge detector that uses two registers on a clk to capture the positive ad the negative edge of the sclk. The edge detector was used along with several logic gates to indicate the sampling and shifting of bits according to the mode that is given. The edge detector enables the Read more

By calvinraveenthran, ago

Week 0001

Hi, my name is Radek and I am the new intern in Aeste Works. The first week has passed during which I was familiarizing myself with the workplace and the task I will be working on over my 3-months-long internship. My job will focus on describing hardware using a strange language that seems to be called Very Log. The language itself seems very primitive and lacks adjectives, so describing anything with it seems to be pretty difficult task but my Read more

By radoslawk, ago
sxc.hu

Diaries of a Useless Intern #1

This week wasn’t the brightest. Our tasks from last week has been dragged to this one which is designing a  GPIO and a wishbone interface and a dummy master to drive the GPIO, the later being my task. It was a cloudy day full of rain and sweat, definitely not the best setting to present your results to your supervisor yet we didn’t heed the warnings of mother nature. The climax was the moment when my supervisor realized that in Read more

By [email protected], ago

Completed GPIO using the Wishbone protocol

In my third week, I worked on designing a GPIO device that uses the wishbone protocol. This project was the same one i was working on last week.  I was able to finish my part this week. My gpio basically consists of a direction register and a data register that are connected to a inout wire. I have several inputs that correspond to the wishbone protocol. These are the data_in, data_out, clk_in, sel_i, we_in, cyc_in and stb_in. the data is Read more

By calvinraveenthran, ago

A stumble along the road

This week hasn’t been the most productive for me. I struggled to finish a simple dummy master to test the GPIO and to successfully connect my interface with the GPIO and make sure that all transactions are wishbone compatible. Having examined my results, my supervisor pointed out the following fatal mistakes: 1- I mixed simulation commands into my verilog devices code. 2- I still think of verilog as software programming and not as Hardware description language. Here is some tips Read more

By [email protected], ago

Second Week: Wishbone SOC

For this week the task is to explore the Wishbone SOC and create a simple interconnect that is wishbone compatible. The interconnect is to be a slave to the processor and contain several masters that control various I/O devices. While learning what I need to do my new task I improved my skills in previously explored topics and came across some nice references. I included those references at the bottom of this article. To learn wishbone SOC I referred to Read more

By [email protected], ago

Designing a GPIO using the wishbone protocol.

For my second week at AESTE, I was assigned to design and implement a GPIO using the wishbone protocol. The wishbone protocol is a standard method that is used by many processors to communicate to their IO devices. It is a format that uses several several signals in its BUS to facilitate the transportation of data to and from IO devices. I was particularly asked to focus on the IO device that adheres to the protocol. Initially my first approach Read more

By calvinraveenthran, ago

First week

My First day started with introducing the workplace and the project I’ll be working on followed by a quick introduction about Verilog and the necessary tools that I need to use to do my work. For this week the goal will be to wrap up all the learning that I need to do and make a blinking LED FPGA design ( basic clock delay using counters and I/O) on Xilinx Spartan X3CS700A mounted on Spartan 3A revision C starter kit Read more

By [email protected], ago