Hi, my name is Radek and I am the new intern in Aeste Works. The first week has passed during which I was familiarizing myself with the workplace and the task I will be working on over my 3-months-long internship. My job will focus on describing hardware using a strange language that seems to be called Very Log. The language itself seems very primitive and lacks adjectives, so describing anything with it seems to be pretty difficult task but my Read more
This week wasn’t the brightest. Our tasks from last week has been dragged to this one which is designing a GPIO and a wishbone interface and a dummy master to drive the GPIO, the later being my task. It was a cloudy day full of rain and sweat, definitely not the best setting to present your results to your supervisor yet we didn’t heed the warnings of mother nature. The climax was the moment when my supervisor realized that in Read more
In my third week, I worked on designing a GPIO device that uses the wishbone protocol. This project was the same one i was working on last week. I was able to finish my part this week. My gpio basically consists of a direction register and a data register that are connected to a inout wire. I have several inputs that correspond to the wishbone protocol. These are the data_in, data_out, clk_in, sel_i, we_in, cyc_in and stb_in. the data is Read more
This week hasn’t been the most productive for me. I struggled to finish a simple dummy master to test the GPIO and to successfully connect my interface with the GPIO and make sure that all transactions are wishbone compatible. Having examined my results, my supervisor pointed out the following fatal mistakes: 1- I mixed simulation commands into my verilog devices code. 2- I still think of verilog as software programming and not as Hardware description language. Here is some tips Read more
For this week the task is to explore the Wishbone SOC and create a simple interconnect that is wishbone compatible. The interconnect is to be a slave to the processor and contain several masters that control various I/O devices. While learning what I need to do my new task I improved my skills in previously explored topics and came across some nice references. I included those references at the bottom of this article. To learn wishbone SOC I referred to Read more
For my second week at AESTE, I was assigned to design and implement a GPIO using the wishbone protocol. The wishbone protocol is a standard method that is used by many processors to communicate to their IO devices. It is a format that uses several several signals in its BUS to facilitate the transportation of data to and from IO devices. I was particularly asked to focus on the IO device that adheres to the protocol. Initially my first approach Read more
My First day started with introducing the workplace and the project I’ll be working on followed by a quick introduction about Verilog and the necessary tools that I need to use to do my work. For this week the goal will be to wrap up all the learning that I need to do and make a blinking LED FPGA design ( basic clock delay using counters and I/O) on Xilinx Spartan X3CS700A mounted on Spartan 3A revision C starter kit Read more
Last week, I was given the opportunity to explore several programs that I needed to use for my upcoming project. These were GIT, Icarus, GTK waveform viewer and finally ISE. I learnt how to store and manipulate files from a repository through GIT. I would recommend GIT to anyone who is interested in software programming. With GIT, you will be able to work on many aspects of a program and merge them when you need to. You could even store Read more
It was fun getting the Zedboard working on Ubuntu 12.04 LTS. We are using 2012.4 version of ISE/Vivado Webpack. There are no major tricks in getting it to work but since there does not seem to be a guide out there, I thought that I’d write a quick one here. Download ISE Webpack from Xilinx here. We are using version 2012.4 here. Unpack the ISE Webpack. $ tar -xf Xilinx_ISE_DS_Lin_14.4_P.49d.3.0.tar Install the ISE Webpack. $ ./Xilinx_ISE_DS_Lin_14.4_P.49d.3.0/xsetup Download the Digilent run-time Read more
I managed to set up physical layer for ethernet connection after solving the error which came from the .c file that end with ‘#endif’. I just needed to add an empty line after ‘#endif’ and that solved the problem. When the board was powered up, the LED D8 was blinking, the green LINK LED on J1 was lit and the LCD display showed the TCP Stack version and the IP address in use by the board. These indicated that the Read more
