Engineering Elegance

A bit more writing and a lot more reading

Following the functionality of the Base64 decoder and CRC checked writing process, it was time to move onto the next step to reach the objective set for the month. The next step is to integrate two specific portions into the current code; i) the Ping-Pong Upload mechanism and ii) Reading out the written data through the UART. Both of these tasks were handled with during the week although with different rates of success. Other than that, it was also time to Read more

By saimoon.quazi@aeste.net, ago

How to control I2C?

This week I’ve fully completed I2C master and slave and tested them by simulation. Having been over that I’ve moved to learning C++ object oriented programming to write the code that creates the system top level code. There isn’t much to say about C++ so I’ll use this blog post as a guide for whoever is going to create drivers for my I2C device in the future. Along with the comments found in my HDL code, I hope this guide Read more

By mostafa@aeste.net, ago

Functional File Upload with Base64 decoder and CRC checksum

This week ended up being highly productive as it culminated into the completed functionality of the file upload system with Base64 decoder and CRC support. However, it was not always plain sailing during the week and much time, effort and attention to detail was needed to debug the existing code. By the end of the week, all aspects of the file upload were debugged and performance tests were run, the results of which can be seen below. Debugging the existing Read more

By saimoon.quazi@aeste.net, ago

I2C Revisited

Finalizing I2C continues. Finally the master is fully functioning but tested only through simulation. Here is the Features of the master: Clock Synchronization and Arbitration. Detection of a busy bus. Supports Arbitration loss. Handles Slave induced waits. Capable of repeated start and back to back reads and writes. Future Improvements: Add support for Various I2C speeds Add support for special I2C addresses Solve the drawn back of the master losing arbitration if the required slave is not present The master Read more

By mostafa@aeste.net, ago

Ahead with the Project

This week was very interesting and yet tiring one! I wrote my networking c++ program and began to understand how machine interacts with each other. That involved too much researching and reading. and most of the time I ended up closed lines. I spent the first few days on researching networks and how to transfer files generated in one machine to another machine which will use it as an input. I wrote my first server and client applications, that moment Read more

By ademi, ago

PIC18 Interrupt Service Routine

The next thing to do is to initialize the interrupt service routine and also to configure the change on Port B interrupt. By referring to the interrupt that is used by the original demo to calculate the ticks for the blinking LED for the TCP/IP stack, it seems that is necessary to set the global interrupt enable pin, set the interrupt priority enabled pin, low priority interrupt enable pin and high priority interrupt enable pin. The change on Port B Read more

By chewjiaxien, ago

Its all about SD cards!

Following the disaster of having the 4gb Kingston SD card stop responding, the focus of the week was to find a way to get the non-responsive SD cards to work on the PICTail. A lot of knowledge was gained about the SD cards initialization process (the process at which some of SD cards stop responding). Debugging the MDD Initialization Stack from Microchip Continuing on from the previous week, debugging was continued on the current Initialization process from Microchip. Following the Read more

By saimoon.quazi@aeste.net, ago

Let the Integration Begin

By the end of this month, I should be able to integrate everyone’s project in to mine, and manage them  to produce the desired output I started with Verilog synthesizer.In this process, I’m supposed to execute a shell script that takes a .v file and runs on it three software ,namely xilings , Ngbuilds and Data2mem, to produce a .bit file that contains the configuration bits for the fpga to implement the design of the user. I finish this task Read more

By ademi, ago

Environment Variables for Xilinx tools

Last week I created a script to run all Xilinx tools required for implementation from the command line. We are using the 14.4 version of Xilinx software. Before using any of the tools in this version a Xilinx script is required to be executed to set required environment variables. However the script sets variables for many Xilinx tools such as Vivado and Plan ahead that are not necessary for our process. Hence, this week I had to dig through Xilinx Read more

By mostafa@aeste.net, ago

MASTER & SLAVE Modes

My next task was to do something to make the PIC able to switch between the MASTER mode and the SLAVE mode. Generally, the MASTER mode will be the mode where the PIC will be acting as a server and will be receiving the bitstream from the Internet and then save the bitstream into the SD card, while the SLAVE mode will be the mode where the PIC will be reading the bitstream from the SD card and send the Read more

By chewjiaxien, ago