This post is a documentation of the final version of automated test benches created to verify our IO cores. The test benches have been created for the our GPIO, Master SPI, Slave SPI, UART & I2C master and slave. The test benches verify only the behavior of those devices within their specs. It doesn’t have any random tests or tests for their behavior out of their specs. Here is an overall explanation of how the test benches work First, each Read more
In the past month I’ve been experimenting with various approaches to create Automated Test Benches to my Verilog IO cores that are using Wishbone bus. The Automated part simply means that the test bench will verify the correctness of the received outputs and display a Pass or Fail message. This is opposing to the normal test benches where a waveform or textual dump of signals is generated and the user has to verify the correctness of the outputs himself. In Read more
We are considering deploying Witty applications on OpenShift. In theory, it should be possible to do it but it’s still necessary to test things out. There are some unanswered questions on how such a deployment might work. This blog entry was very useful in getting things deployed on a DIY cartridge. However, there are some minor issues that needed to be tweaked. Starting The start action hook that I used was: nohup $OPENSHIFT_REPO_DIR/diy/hello.wt –http-port=$OPENSHIFT_DIY_PORT –http-address=$OPENSHIFT_DIY_IP –docroot=$OPENSHIFT_REPO_DIR/www |& /usr/bin/logshifter -tag hello.wrt Read more
Verilator does a great job notifying you about any possible source of error in your Verilog code. However, it’s not really the best sight getting a screen full of assorted warnings and errors whenever you compile a code with Verilator that was just working perfectly on Icarus. I don’t like warnings so I shot them down one by one until Verilator had absolutely nothing to say. This blog explains a couple of tough warnings that I had to figure out on my Read more
In order to test my GPIO design whose width can vary from 1 to 64 bits I need to be able to generate random values to properly drive it’s data line. I need a method that’s fast and fairly random as it will run for many repetitions. Before that I’ve used the verilog $random function and it behaves very good when you supply it with a random seed but it’s limit is 32 bits I think. I could have concatenated Read more
As part of my efforts to create “perfect” test benches I am to make sure the test benches work when compiled with different simulators. This approach is to expose language errors and any bugs in one of the simulators. Hence, I’ve tried to compile my test bench with Verilator and the process wasn’t as easy as I expected it to be. In this post I’ll give an overview of Verilator focusing on how it’s different from Icarus Verilog. The main difference stems from Read more
In the previous post, Testing like a Pro, I explained some general guidelines to thoroughly verify the behavior of an RTL design. I’ve been working on the test bench for the GPIO over the past week. In this post I’ll explain it’s features and give a block diagram to two ways that can be used to implement this design. The GPIP new automated test bench have the following features: It’s basic testing sequence is it sets the GPIO direction, writes Read more
We are now using XCFE in Aeste, probably because it’s supposed to be a “light” desktop environment. However, I didn’t fancy it’s looks and absence of keyboard shortcuts similar to Ubuntu. Hence I took some time to make my desktop environment usable and setup some keyboard shortcuts. You can find out how to setup shortcuts from here. Here is a list of the ones that I set and their command names Applications Menu /usr/bin/xfce4-popup-applicationsmenu Take a screenshot xfce4-screenshooter -f Open Read more
This is my last post for the entire internship that I had gone through in AESTE Works. To sum up the work for this week, I did the cleanup and pushing to Github. The porting of FreeRTOS to the latest AEMB2 was not yet complete, but most of the relative issues had been identified and fixed. The interrupt mechanism used during critical regions might not be useful and maybe the next person to take over from me can think of Read more
