Registers for UART, SPI and TWI

This week Dr Shawn has explained to me the internal registers of UART, SPI and TWI. Basically these modules has two registers: status register and data register. Status register, from its name we know that this register contains information about the state of the device. Data register contains the data to be stored or to be fetched. For each module, I need to implement flags to check the status of the device whether it is ready to perform data transmission Read more

UART in Simulator

This week I am working with UART (Universal asynchronous receiver/transmitter). UART is a device that used for serial communication over a peripheral device serial port or computer. UART takes bytes of data and transmits the individual bits in a sequential fashion. UART consists of a data bus with several data lines (usually 8) with control pins for read/write and two serial wires which are TX (Transmit) and RX (Receive). Note that the connection between UART must be carefully and correctly connected. Read more

Configure FPGA with slave serial method

This week I try to fix ‘init_b’ low and get the configuration of spartan 6 working. ‘init_b’ turn high Finally manage to read a HIGH output from ‘init_b’ of FPGA. The solution was to have PIC32 enabled ‘pull_up’ on the input pin and some additional pic32 initialization set up. Next is to toggle ‘program_b’ to check whether ‘init_b’ will go low (following the data timing of ug380), and indeed it works. SPI initialization Based on the example of ‘spi_loopback’ from Read more

Software Test

Software test is all about breaking the application, which can be hard sometimes when there is an emotional attachment. My colleague Peter and previous interns working on the project have done a great job and their code is working fine. For my part, i need to make sure p3muka, the user project management application does its job. Http::Client and Curl Before the access_token expires, a batch project file sync is initiated. Since the upload is handled completely by WResource, it Read more

Progress bar and Storage Mechanism

Progress bar I started this week with implementing a progress bar on the code editor component to indicate the status of a background process. I always thought that progress bars were cool, especially the one used by YouTube. Luckily for me i did not have to built one from scratch. NProgress bar has it all sorted out for me. Being a leech, all i had to do was include the script and use it. On top of basic usage, such Read more

Init_B Forever Low

This week I try to configure the FPGA using PIC32 with slave serial method. C array bit file First I convert the binary file of FPGA into C array (Hex format) so that I could use SPI 8bit or 16bit to send the hex data bits by bits into FPGA. Using linux terminal the below command was used to convert bit file. xdd -i your.bit Besides that, ‘Hexdump’ can also be used to convert bit file to hex format but Read more

Master SPI

This week, I have been trying to complete the Master SPI module (MSPI) as soon as possible. In the simulator, the MSPI is suppose to send data to a device and/or read data from a device. This can be done by using the same function. I created a ‘transfer’ function in which it can store or read the value passed into the function. This week I did some study on how to detect the connection status of MSPI ports, where the MOSI, Read more

New features and Improvements

Browsers compatibility Last week, I found out that a crash occurred when using Mozilla instead of Chromium browser, which was caused by a memory fault. I was passing a variable from one session to another in the application: In chromium, there was no issue as the first session was destroyed only after a timeout set in wt_config; In Mozilla, the session was immediately destroyed without timeout as the user exits the session. Anyway, my method of retrieving the variable was Read more

OSI with PIC32 and LAN8720

This week I continue testing the board. Trying to fix the OSI layer of PIC32 with LAN8720. Studying different board behavior with same code I first started with programming the rest of the board with the same code and realize that the current board I am using have a different behavior compare to the other 4. In other words, with probability and statistic the board I am currently using should be faulty while the other 4 are fine, with that Read more

The Final Task

This week is my last week of work as a part time engineer. I focused on the previous task that had been given, which is to develop a simple Verilog design. The Final Task Since the last task is to design a Verilog module, which I have not been doing it since the demosaic modules. Just like what I previously done, I drew out the circuitry that I am going to infer on using Verilog, and examine the signals. The design Read more