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One step closer

Fourth week of internship. As Dr Shawn advised me to modify the repository, I had to study the code carefully so that I could be able to generate a correct top level verilog file for synthesis. To do so, it was crucial to understand std::map, as most of the important information was stored in a map. Std::map was an associative container to store elements, i.e. key-value pairs. A simple example would be std::map<int, int> map, where the map stored key-value Read more…

‘Tis the season to be jolly

This week is the week where I try to finish up all of the basic functionalities of the application. What I had left was to figure out how to create a custom x509v3 extension with Botan C++. As recommended by Dr Shawn, I used the UserRole extension, as shown here. Creating the UserRole extension with Botan C++ involves having a self-defined class to inherit the properties of Botan’s Certificate_Extension class. Since it is an abstract class, there are some methods Read more…

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Week Three

This is week three of my internship at Aeste Works. Three main tasks were assigned to me this week. First was to study on the programming & configuration protocols of three different FPGA’s namely Xilinx’s Spartan-6, Intel’s Cyclone and Lattice’s iCE40. Currently, the company’s own board incorporates the Xilinx Spartan 6 FPGA configured by a PIC32 microcontroller and thus the objective of studying the documentation of the other two were to determine whether or not a different configuration protocol will Read more…

Diving right into Synthesis

In this week I was experimenting with Yosys. Yosys was a Verilog HDL synthesis tool. A synthesis would automatically convert a high-level representation of a circuit to that of a low-level representation. The behavioral design description would be an input for Yosys and it was able to generate a register-transfer level (RTL), logical gate and physical gate level description. Its main purpose, however, was to perform behavioral and RTL synthesis. In addition, there were several FPGAs which could be synthesized Read more…

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Getting there, I hope…

The major thing that I managed to get done by this week was the implementation of interfacing with the WooCommerce REST API. As a reminder, this is only done by the application when a new subscription for an organization certificate is made, and the customer also chooses the option to entrust the management of their certificate to us, hence their intermediate CA certificate will be stored on our server side. This intermediate CA is responsible for issuing client certificates that Read more…

Week Two

This was the second week being an Intern at Aeste. At the start of the week, Dr Shawn explained the overview of the main project that I would be handling during this internship. One of the tasks were to eventually interface a few other popular FPGA’s with the PIC microcontroller on the board aside from the already interfaced Xilinx Spartan FPGA. This would require investigation and research on the required information such as bitstream format as well as programming protocols. Read more…

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A week with Verilog

In this week, I was mainly dealing with Verilog. Verilog was a hardware description language (HDL) and it was used to describe a digital system. Firstly, I tested out a 8-bit simple up counter and ran it within the terminal. The code was comparable to Altera Quartus II. I had experience with Verilog previously and hence I was very familiar with its implementation. In addition, I tested out a simple AND gate, a comparator, a 3-to-8 decoder and a multiplexer. Read more…

Enduring the Groundwork

This week was all about catching up. The project that I will be working was introduced this week by Dr Shawn which looked both interesting and challenging at the same time. I was assigned to upgrade and improve the functionality of two main parts in an existing design software. As the project was previously worked on by other interns, I spent a large amount of time understanding and catching up to fully grasp it in order to effectively improve its Read more…

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Certificate Revocation Lists (CRLs)

This week, I made one more step of progress by implementing the Certificate Revocation List (CRL). The CRL holds a list of certificates that had to be revoked before their expiry date for a particular reason. In our case, that reason would be to handle the case where the customers can make early renewals for their subscription. But because they are already holding a valid certificate from their last payment date, we would need to revoke that certificate and supply them Read more…

Week One

This was the first week being an Intern at Aeste. One of the tasks given this week was to learn about Git. It’s a version control system primarily used to efficiently manage code in software development. There are a lot features that makes Git a powerful management tool. We can ‘commit’ any change we’ve done on a ‘branch’ we’re working on.  Lots more Git features were tested on a sandbox Git repository to further our understanding on how Git works. Read more…

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