Engineering Elegance

EDK63 Mode Activation

There are several methods that can be employed to enable/disable special operating modes of the AEMB. The most obvious method would be to set/clear special bits within the MSR register using the standard instructions. However, there is another method of doing it that may be employed. Firstly, it is possible to use any branch instruction to activate or de-activate any special mode. All branch targets are meant to be word-aligned. Therefore, any non-aligned branch could be used for this purpose. Read more

By Shawn, ago

EDK63 Thread Independence

The EDK62 core introduced multi-threaded capabilities to the AEMB2 in the form of fine-grained multi-threading using a barrel processor. Essentially, it interleaves and alternates the instructions for the two threads on each clock cycle. However, the two threads are inter-locked, which means that one blocking thread will block the other thread as well. Thread Dislocation This problem reduces the performance of the AEMB2. Therefore, the EDK63 core will unlock the two threads so that one blocking thread does not block Read more

By Shawn, ago

EDK63 Cache Memory Block

Resource efficiency is always a goal of the AEMB2 design. In order to further reduce resource consumption and improve operating speed, some minor changes are being made in the next generation EDK63 core architecture. The first block to experience some changes is the cache memory block. Looking at the numbers for the EDK62 core, the tag memory block uses 3% (74/2444) of the total core resources. With an additional data cache planned for the EDK63 core, this will increase. Furthermore, Read more

By Shawn, ago

EDK63 Design Considerations

Work has started on a the new AEMB2 core processor. This processor is targeted to be EDK6.3 compatible. However, there are a few major changes planned for the release of the E63 core. There is a great amount of both hardware and software work involved. Therefore, this release will take much longer than previous releases have taken. Hardware The following are a few new hardware features to look forward to. Data Cache – A compulsory data cache will be added. Read more

By Shawn, ago

Next-Gen AEMB Update

Several months have passed since development on the next generation AEMB core started. During this time, there has been some experimentation on features and architecture, as well as design considerations made, to improve the performance of the core. Some improvements were made to accommodate the ability to execute dual-threads in hardware, while others were made to speed up the pipeline. The major changes are listed below: Upgraded compatibility of core to EDK 6.2 compatible. Integrated on-chip instruction cache memory. Added Read more

By Shawn, ago

Next Generation AEMB Development

A new AEMB core is in the works. It will feature a radical departure from the present compatible architecture, while maintaining software compatibility. It has twice the clock rate of the present core and can execute two hardware threads. There are also other improvements made to the core. Initial results have been extremely promising, delivering a doubling in code performance. After the development of the AEMB 7.11 got wrapped up, there were many ideas floating around, on things to improve. Read more

By Shawn, ago

AEMB 7.11 Released

This release marks a major mile-stone in the AEMB project. It is 99.9% EDK3.2 software compatible with the addition of get/put, barrel-shift and multiply instructions. It has stable interrupt support for working with external I/O devices. Also, it features a major rewrite of the core to fix all the previous bugs found. This release marks a major mile-stone in the AEMB project. It is 99.9% EDK3.2 software compatible with the addition of get/put, barrel-shift and multiply instructions. It has stable Read more

By Shawn, ago