Engineering Elegance

Next-Gen AEMB Update

Several months have passed since development on the next generation AEMB core started. During this time, there has been some experimentation on features and architecture, as well as design considerations made, to improve the performance of the core. Some improvements were made to accommodate the ability to execute dual-threads in hardware, while others were made to speed up the pipeline. The major changes are listed below: Upgraded compatibility of core to EDK 6.2 compatible. Integrated on-chip instruction cache memory. Added Read more…

By Shawn, ago

Next Generation AEMB Development

A new AEMB core is in the works. It will feature a radical departure from the present compatible architecture, while maintaining software compatibility. It has twice the clock rate of the present core and can execute two hardware threads. There are also other improvements made to the core. Initial results have been extremely promising, delivering a doubling in code performance. After the development of the AEMB 7.11 got wrapped up, there were many ideas floating around, on things to improve. Read more…

By Shawn, ago

AEMB 7.11 Released

This release marks a major mile-stone in the AEMB project. It is 99.9% EDK3.2 software compatible with the addition of get/put, barrel-shift and multiply instructions. It has stable interrupt support for working with external I/O devices. Also, it features a major rewrite of the core to fix all the previous bugs found. This release marks a major mile-stone in the AEMB project. It is 99.9% EDK3.2 software compatible with the addition of get/put, barrel-shift and multiply instructions. It has stable Read more…

By Shawn, ago