Engineering Elegance

AEMB on Altera with uC/OS-II in China

Seems like there are three important pieces of news to report: that the AEMB has made in-roads into China; that the AEMB has been implemented on Altera hardware; and that the AEMB is capable of booting uC/OS-II. According to the information provided at a Chinese media website, a key Chinese university (Shandong University of Science and Technology) has successfully implemented an SoC system using the AEMB on an Altera platform and boots uC/OS-II. They published a paper on this earlier Read more…

By Shawn, ago

Virtual Kernel

While everyone seems to be quite focused on high-end virtualisation, there is also room for virtualisation solutions at the low-end. One way of approaching this problem is by the use of a thin layer of virtualisation at the nano-kernel level. Instead of just abstracting hardware away, it is also possible to put in entirely virtual hardware devices for embedded applications. This allows things like I/O peripherals to be abstracted and run entirely as pure software only. The AENIX kernel will Read more…

By Shawn, ago

Power Optimisation

Since the recent LLVM 2.7 release came with initial support for the Microblaze, it is now conceivable to add some features into the LLVM to enable power optimisation for the AEMB and other architectures. The reason that LLVM is chosen instead of GCC is purely subjective – a cleaner code base and the open license adopted. The idea of power optimisation lies behind the premise that power is a systems level problem – not a hardware one. While hardware is Read more…

By Shawn, ago

New Multi-Threading Model

In order to streamline the new AEMB processor family, a new multi-threading model is being tested. In the new multi-threading model, each core will have at least the capability of running four threads either manually or automatically. For the AEMB1, the threads would need to be switched explicitly using special software break instructions while for the AEMB4, the context switching will happen automagically and the AEMB2 will be somewhere in between the two. As for the software, the AEMB1 will Read more…

By Shawn, ago

In-Cache Execution Environment

The AEMB is designed with an FPGA target technology implementation. Since this is the case, it may be prudent to exploit certain FPGA capabilities that are not present on ASIC technologies. One such capability is the ability of an FPGA to pre-load the contents of block memories from an FPGA image. This ability is often used to create a read-only RAM block or ROM block. However, if the write-enable signal is enabled this ability can be used to pre-load the Read more…

By Shawn, ago

Conjoining Resources

Since increased concurrency seems like the way to go for computing, I am interested in increasing the concurrency of the AEMB from 2 to 4 hardware threads. This can be done through a dual-core set up. However, I plan to make my dual-core AEMB special by sharing resources between them so that it doesn't actually cost twice the amount of chip resource to implement two cores. So, it is more like having the power of two cores at the cost Read more…

By Shawn, ago

Compiler Futures

At present, all software is compiled using a custom GCC compiler backed by binutils and newlib. However, as the AEMB processor is sufficiently different from the original architecture, it may be time to start porting a new compiler to it. At the moment, the regular GCC compiler is used (with some software hacks) but the architecture can only diverge further in the future. Therefore, steps are underway to build a custom port of a compiler. The leading candidate of choice Read more…

By Shawn, ago

Microkernel Considerations

I have been thinking about implementing some sort of OS on the AEMB. At the moment, the OMRP people have had some success with running a uCLinux OS on the AEMB. However, using uClinux may be a bit excessive for simple projects. Therefore, I have thought of implementing some form of micro-OS on the core. I have already written a simple boot-strap programme that checks the memory for errors. It is a simple programme that can even fit entirely inside Read more…

By Shawn, ago

Kernel Mode

While thinking about the idea of using a micro-kernel, the idea of introducing a special 'kernel mode' came about. However, unlike other processors, this kernel mode does not expose any special instructions. The idea is to switch the instruction execution from external code to internal code. When the processor first boots up, it should start by running the boot-loader, which is located internal to the core. This boot-loader will then run a memory-test routine to ensure that memory is not Read more…

By Shawn, ago

EDK63 Virtual Peripherals

As mentioned earlier, the idea of virtual peripherals is quite tempting on the AEMB core. The two independent hardware threads can be used to implement a single threaded application along with a second thread performing maintenance functions such as interrupt handling. It is therefore possible to implement some hardware peripherals in software. The reason for this idea is the target market of the core. The AEMB is targeted at small and resource efficient FPGA implementations. It is often used in Read more…

By Shawn, ago