Chronicles from our peeps.
I’ve implemented a list of tests for each device to test it’s behavior within specifications. Those tests are specific for each device. The set of tests is repeated for each possible value of the tested device parameters and each run with new parameter values has it’s expected output saved in Read more…
The ultimate future goal is to create a generic Automated Test Bench that can be used with any of our IO cores. Of course the test vectors testing each core has to be different. However, since all our cores use wishbone bus this simplifies creating a generic solution. In this Read more…
In the past month I’ve been experimenting with various approaches to create Automated Test Benches to my Verilog IO cores that are using Wishbone bus. The Automated part simply means that the test bench will verify the correctness of the received outputs and display a Pass or Fail message. This Read more…
We are considering deploying Witty applications on OpenShift. In theory, it should be possible to do it but it’s still necessary to test things out. There are some unanswered questions on how such a deployment might work. This blog entry was very useful in getting things deployed on a DIY Read more…
Verilator does a great job notifying you about any possible source of error in your Verilog code. However, it’s not really the best sight getting a screen full of assorted warnings and errors whenever you compile a code with Verilator that was just working perfectly on Icarus. I don’t like Read more…
In order to test my GPIO design whose width can vary from 1 to 64 bits I need to be able to generate random values to properly drive it’s data line. I need a method that’s fast and fairly random as it will run for many repetitions. Before that I’ve Read more…
As part of my efforts to create “perfect” test benches I am to make sure the test benches work when compiled with different simulators. This approach is to expose language errors and any bugs in one of the simulators. Hence, I’ve tried to compile my test bench with Verilator and the process wasn’t Read more…
In the previous post, Testing like a Pro, I explained some general guidelines to thoroughly verify the behavior of an RTL design. I’ve been working on the test bench for the GPIO over the past week. In this post I’ll explain it’s features and give a block diagram to two Read more…
We are now using XCFE in Aeste, probably because it’s supposed to be a “light” desktop environment. However, I didn’t fancy it’s looks and absence of keyboard shortcuts similar to Ubuntu. Hence I took some time to make my desktop environment usable and setup some keyboard shortcuts. You can find Read more…
This is my last post for the entire internship that I had gone through in AESTE Works. To sum up the work for this week, I did the cleanup and pushing to Github. The porting of FreeRTOS to the latest AEMB2 was not yet complete, but most of the relative Read more…