I basically did the text processing part on the first day of this week. By using regex, the program is able to read through a template and output the signals’ name on a Verilog file. But this technique is not suitable as the user has to make sure that the device is compatible with the template.
I basically spent most of the time studying JointJS before I get to talk to Dr. Shawn. We realized the problem of reading the auto-template on Friday and Dr. Shawn patiently explain the flow of design to me. I understand that there are mainly three parts that I have to focus on which are the arrangement of IO devices and assigning address to them, naming convention for the wishbone signals, and the IO signals.
Dr. Shawn told me about the way a previous intern utilized to implement the switch design. For now, I finish the part where I have to assign address to each IO devices and arrange them in an alphabetical order. Next, I need to figure out a way for the AUTOINST feature in Verilog-mode to label each signals’ name according to the device’s name.
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