This week has been a roller-coaster ride for me. There were times when Wt just refused to be a good sport, times when we made great and wonderful progress and also times when I thought Wt wronged me, but turned out I did not understand it enough. As usualy, I Read more…
Finally, after weeks of working on the demosaic core on software simulation, the real hardware implementation starts! The week went with the couple of frustrations on debugging the Xilinx PlanAhead tool, and the excitement on implementation of demosaic core on FPGA. 😆 😆 😆 Using Zedboard to Test the Core This is the first Read more…
Continue from the previous blogs, this blog focus on debugging the upcoming errors that may be faced on while using the Zedboard. These errors are the bugs from the Xilinx PlanAhead 14.4, 2012 late version, working on Ubuntu 14.4 operating system. XPSGuiSessionLock Error Initially, I was following the Zedboard CTT ISE 14.4 Read more…
This is my thirteen week in AESTE. Getting closer and closer to the end of my internship~ This week I continue with drawing Schematic. 😴 💤 💩 😈 👿 👹 👺 💀 👻 👽 🙌 👏 👋 👍 👊 ✊ ✌️ 👌 ✋ 💪 🙏 ☝️ 👆 👇 👈 👉 Nothing Read more…
Finally, this week I finished on the schematic of the whole demosaic core, described it in Verilog, and simulated it using the Icarus Verilog simulator. In the path of implementation, many problems occurs and it was really interesting to tackle them. The Edge of Bilinear Interpolation Bilinear interpolation is a simple Read more…
For the whole week, I’ve been continuing work on my task, which is to build some sort of project manager interface. Last week, I built a simple interface without much functions. So, what I did is mostly creating functions and improving the graphical interface. Requests, requests and more requests As Read more…
This is my twelve week in AESTE. Continue fixing some minor bugs for my JQuery with Wt and many studying and planning for my PCB design. Getting Started with having SERVER sending request to CLIENT First I change my ‘CUSTOM’ request into ‘HEAD’ request, and have my SERVER (PIC32 in Read more…
This is my eleventh in AESTE. Trying to use Witty (Wt) as a CLIENT to send request to my PIC32 wolfSSL server. My time limit is 3days to get this done. ̿̿ ̿̿ ̿̿ ̿̿ ̿’̿’\̵͇̿̿\з=( ͡° ͜ʖ ͡°)=ε/̵͇̿̿/’̿’̿ ̿ ̿̿ ̿̿ ̿̿ Read more…
This week, things are getting clearer, and the work are getting better. I began to realize my previous mistake, that the image processing pipeline core might be driven in different clock speed, compared to the CCD clock speed. The core should be able to drive as close as the CCD Read more…
This week, Dr. Shawn gave me a briefing on my new project. It seems quite a hefty task for me, but I hope I can finish it in time. FYI, I am working on a some sort of online project manager with user identification. The first thing I started working Read more…