SPI bug, timing and documentation

Finalizing continues with the SPI. I have previously made a few changes in SPI while integrating it with the system but I hadn’t verified the functionality of SPI after those changes. The most notable change was that one of my if statements was mistakenly inferring a latch. The if statement was missing an else condition. I tested the SPI and it performed as intended on simulation and FPGA. Moreover, I tested the SPI driver. While the FPGA implementation wasn’t very smooth it did prove that the driver is functional. As with the gpio driver, I had to add the include guards for the SPI driver. Most probably I need to do this for all our drivers for accelerators.

The optimum choice of optimization levels for the synthesis process is having the XST run at effort level 1 (medium) and both the MAP and PAR run at low effort level. The Synthesis tool has to run at this level to meet the timing constraints and create a design which can operate at 100 MHZ of clock. It took me a while to verify that the design can run at a 100 MHZ after MAPing and PAR. The reason is because as usual the guides and some of the data sheets that I come accross are outdated with respect to the Xilinx software we are using. My last resort was to set a constraint on the maximum delay path period and see if the design meets it. The results were positive.

I’ve started fixing the bugs in the accelerators and finalizing the UART device.

Finally, here is the block diagrams for the remaining devices and the SOC.