By the end of this month, I should be able to integrate everyone’s project in to mine, and manage them to produce the desired output
I started with Verilog synthesizer.In this process, I’m supposed to execute a shell script that takes a .v file and runs on it three software ,namely xilings , Ngbuilds and Data2mem, to produce a .bit file that contains the configuration bits for the fpga to implement the design of the user.
I finish this task as fast as possible, as I discovered a nasty bug in one of my code I wrote earlier. It was about displaying error messages to the user indicating the flows of his/her code. While coding I was so involved with the user writing faulty messages, that I forgot to test the case where the user writing fault free code.
the next step will be processing that .bit file to get it ready to be downloaded to the Fpga by a Pic micro controller, I hope this task would be as pleasing as the the Verilog Synthesizer, though I doupt it as working with binary numbers is not that amusing .
See you next weekend 🙂
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