As I am collecting the statistic of how the TCP receiver buffer size affects the speed of downloading, I found that the time it takes to download the firmware topped at around 11.6 seconds with 512byte of receiver buffer size, which is in fact very slow, further increase of receiver Read more…
Last week after finishing the schematics I started with assigning and creating the components footprints. This was the first thing I finished this week, though it took some time to finish them. Afterwards, I started with placing the components on the board. Placing Components First things first; our board is Read more…
Now for real, the circuit is finished, and I have started with assigning and creating the footprints for the components. There are no one major updates this week, but rather a lot of changes and modifications to the schematics. As usual, here is the visual diff for this week. Additions Read more…
Good news everyone, the circuit is finished 😀 ! Well, not so fast! Now everything is connected, but there are some last minute modifications to the circuit that were introduced just now. I will work on those first thing next week, and hopefully, I will start with the PCB layout. Read more…
I was interested to find out how much storage is needed to store the bitstream of a minimal design for a Spartan6 FPGA. The minimal design chosen is just a straight-forward 8-bit binary counter. The results are: LX25 Raw/Compressed: 801556/233934 LX16 Raw/Compressed: 464290/134942 LX9 Raw/Compressed: 340697/118773 The sizes stayed the Read more…
I continues working on the schematics this week. By now, almost all the major components in the circuit are connected. Last week I connected the Ethernet jack, SD card, and some of the microcontroller connections. This week I did the connections for the USB port power pins, FPGA I/O ports, Read more…
Another week, another intern. I started on 28 June and was told by my supervisor that I’ll be working mainly with Jia Xien in contributing to the hardware and firmware aspects of Aeste’s current project. After going through the basic tutorials on Git and C, I dove right into my task of the week: researching and weighing configuration interfaces for an FPGA. If you’re feeling an onset of TL;DR-itis, feel free to skip to the last paragraph.