Engineering Elegance

The big picture and saving time

The project becomes closer to completion with the top level creator being as done as possible. In this post I’ll start by explaining the top level creator and it’s awkward status of being “as done as possible”. Next, I’ll try to make the big picture of our project clearer by explaining the whole process step by step. Most importantly, I’ll showcase my results from analyzing the time consumed by the execution of Xilinx tools using various options. The top level Read more…

By [email protected], ago

Continuing Optimization

The optimization of the firmware continued with the focus being on the SD card reading stack. A look into the USART’s synchronous mode functionality was also taken to try and understand how that works. There was also a lot of time spent trying to set up scenarios to break the upload mechanism and see how the system behaves under non-standard conditions. USART synchronous mode The term USART stands for “Universal Synchronous Asynchronous Receiver Transmitter”. So far, only the “Asynchronous” functions Read more…

By [email protected], ago

And the optimization begins!

Following the completion of the Ping-Pong Upload mechanism, its time to step forward to system optimization for the PIC firmware. This includes many separate portions looked into during the week to try to enhance the system performance and deliverable. The tasks include: i)optimization of the read/write functions ii) clearing up flash memory for future firmware updates. Apart from that, it was also required to find possible flaws in the current code which may result in the stack to not function Read more…

By [email protected], ago

Bit streams, Synthesizer and Data2mem

My journey with C++ continues with three engines up and running. The bitgenerator, the software encoding bitstreams to suit our system. The software loader which runs data2mem to load the elf file into the RAM blocks on the bitstream. Last but nor least the synthesizer which runs Xilinx command line tools to transform the Verilog design into a bitstream. Picking up from last week, the software encoding the bitstream , bitgenerator, wasn’t supposed to use the Boost library to do Read more…

By [email protected], ago

Completed Design for the Ping Pong Upload Mechanism

As mentioned last week, the basic logic for the mechanism was devised within the PIC but it needed to be integrated to store and receive information on where the correct version of the file is saved onto the SD card from the card’s MBR itself. The biggest challenge to this problem was to safely store information onto the MBR of the SD card so that it is not damaged in the process. The MBR(Master Boot Record) is the boot sector at Read more…

By [email protected], ago

Playing around with Bit streams

For a short period of time I’ll be writing a couple of C++ programs to do some tasks in our project. The first of them is what took my time this week and it’s more or less playing around with a bit stream. In this post I’ll explain what are the changes required for the bit stream and the reason behind them. Moreover, I’ll explain how my code works for now. A bit stream is the final output from software Read more…

By [email protected], ago

Slave Modules Functionality Tests

The test proceed into testing whether the slave modules are able to perform at high speed, without manual inputs. First, I initialize the Python code on the RPi to 25 MHz and I try to verify the functionality of the module. But, before that I found the ADC modules has been displaying extra bytes of “0b00 0b00” at the terminal. I initially thought it was a part of the program and until I asked Kin Wai about it, and it Read more…

By chewjiaxien, ago

A bit more writing and a lot more reading

Following the functionality of the Base64 decoder and CRC checked writing process, it was time to move onto the next step to reach the objective set for the month. The next step is to integrate two specific portions into the current code; i) the Ping-Pong Upload mechanism and ii) Reading out the written data through the UART. Both of these tasks were handled with during the week although with different rates of success. Other than that, it was also time to Read more…

By [email protected], ago

How to control I2C?

This week I’ve fully completed I2C master and slave and tested them by simulation. Having been over that I’ve moved to learning C++ object oriented programming to write the code that creates the system top level code. There isn’t much to say about C++ so I’ll use this blog post as a guide for whoever is going to create drivers for my I2C device in the future. Along with the comments found in my HDL code, I hope this guide Read more…

By [email protected], ago

Functional File Upload with Base64 decoder and CRC checksum

This week ended up being highly productive as it culminated into the completed functionality of the file upload system with Base64 decoder and CRC support. However, it was not always plain sailing during the week and much time, effort and attention to detail was needed to debug the existing code. By the end of the week, all aspects of the file upload were debugged and performance tests were run, the results of which can be seen below. Debugging the existing Read more…

By [email protected], ago