Unfortunately this week has been the least productive for me. In this post, I will summarize my small progress for this week. More importantly, as the blog title suggests, I will post images of AEMB design that I drew during my analysis. I hope this can make up for my slow progress.
(more…)
It turns out that understanding how web technology works is a hindrance to working with the Witty framework. I keep trying to relate the framework workings to the underpinning web technologies. However, what I should do is to just accept the framework as it is.
(more…)
In my second week, time was an issue. Therefore, I attempted to finish up more this week (my third week) so that I can cover the workload from week two. Generally, I am supposed to finish the opcodes by the end of this week. However, like 99% of the things with programming, it always ends up as an underestimation.
(more…)
In my second week, time was an issue. Therefore, I attempted to finish up more this week (my third week) so that I can cover the workload from week two. Generally, I am supposed to finish the opcodes by the end of this week. However, like 99% of the things with programming, it always ends up as an underestimation.
(more…)
For my second week, I couldn’t work as much as I imagined. After finishing the basic utilities and a general understanding of what I needed, I set off to write the opcodes. The opcodes require more time and effort because ultimately I would like to get it right the first time. However, that requires a general understanding of the aeMB processor.
(more…)
The journey of analysing AEMB is finally reaching a destination. In this post I will discuss AEMB’s interface with the data memory and with the accelerator bus. Moreover, I will explain the design of the execution unit and highlight some of it’s parts that I can’t comprehend yet. Finally I will describe the Branch Condition Checker (BRCC) unit. The Data interface module is responsible for handling the wishbone communication with the data memory. It issues all the wishbone signals and Read more
Dissecting AEMB continues. In this post I will give an overview about the instruction set architecture (ISA) of the AEMB and its register file. Finally I’ll explain how AEMB communicates with the data memory and the accelerator bus. Since AEMB code is compiled using the Microblaze toolchain, the ISA of AEMB is pretty much the same ISA for the Microblaze EDK 6.3. Instructions are all 32 bits and they come in two types. Type A have two source registers, A Read more
Over the past weeks I’ve been exploring the architecture of microprocessors in general and AEMB’s in particular. I wish I can say I am done with dissecting AEMB but I ain’t. In this blog post I will give a quick overview about my project and give a functional description of the modules I managed to grasp in AEMB. My project is to create a few versions of the AEMB. The first version is an adjustment to the threading model of Read more
My first week started with tons of reading. I read about the architecture of MicroBlaze. Shawn also told Mostafa and I about the difference between MicroBlaze and AEMB. The most important thing to note is the process of running multiple threads concurrently. I must be able to implement that with the simulator. Nice to meet you Mostafa 🙂 Since the s3laku will be coded from scratch, I also studied various microprocessor simulators’ code. I was able to identify the main Read more
As we are developing a new web application, the question of which framework to use came up. There are many great frameworks around such as cakephp, django, ruby on rails, etc. However, we ended up settling on Witty for one simple reason – all the people we hire know C/C++ as it is the main development language used in-house. Furthermore, this framework looks extremely powerful as well – able to adapt (live) to a whole range of devices. Installing the Read more