Engineering Elegance

Witty on OpenShift

We are considering deploying Witty applications on OpenShift. In theory, it should be possible to do it but it’s still necessary to test things out. There are some unanswered questions on how such a deployment might work. This blog entry was very useful in getting things deployed on a DIY cartridge. However, there are some minor issues that needed to be tweaked. Starting The start action hook that I used was: nohup $OPENSHIFT_REPO_DIR/diy/hello.wt –http-port=$OPENSHIFT_DIY_PORT –http-address=$OPENSHIFT_DIY_IP –docroot=$OPENSHIFT_REPO_DIR/www |& /usr/bin/logshifter -tag hello.wrt Read more

By Shawn, ago

Dear Verilator, Please Shut up!

Verilator does a great job notifying you about any possible source of error in your Verilog code. However, it’s not really the best sight getting a screen full of assorted warnings and errors whenever you compile a code with Verilator that was just working perfectly on Icarus. I don’t like warnings so I shot them down one by one until Verilator had absolutely nothing to say. This blog explains a couple of tough warnings that I had to figure out on my Read more

By [email protected], ago

Generating 64-bit Hexadecial Numbers with Bash

In order to test my GPIO design whose width can vary from 1 to 64 bits I need to be able to generate random values to properly drive it’s data line. I need a method that’s fast and fairly random as it will run for many repetitions. Before that I’ve used the verilog $random function and it behaves very good when you supply it with a random seed but it’s limit is 32 bits I think. I could have concatenated Read more

By [email protected], ago

Verilator Explained

As part of my efforts to create “perfect” test benches I am to make sure the test benches work when compiled with different simulators. This approach is to expose language errors and any bugs in one of the simulators. Hence, I’ve tried to compile my test bench with Verilator and the process wasn’t as easy as I expected it to be. In this post I’ll give an overview of Verilator focusing on how it’s different from Icarus Verilog. The main difference stems from Read more

By [email protected], ago

GPIO Automated Test Bench

In the previous post, Testing like a Pro, I explained some general guidelines to thoroughly verify the behavior of an RTL design. I’ve been working on the test bench for the GPIO over the past week. In this post I’ll explain it’s features and give a block diagram to two ways that can be used to implement this design. The GPIP new automated test bench have the following features:  It’s basic testing sequence is it sets the GPIO direction, writes Read more

By [email protected], ago

Testing like a Pro

We are now using XCFE in Aeste, probably because it’s supposed to be a “light” desktop environment. However, I didn’t fancy it’s looks and absence of keyboard shortcuts similar to Ubuntu. Hence I took some time to make my desktop environment usable and setup some keyboard shortcuts. You can find out how to setup shortcuts from here. Here is a list of the ones that I set and their command names Applications Menu /usr/bin/xfce4-popup-applicationsmenu Take a screenshot xfce4-screenshooter -f Open Read more

By [email protected], ago

Final Week and Some Impressions

This is my last post for the entire internship that I had gone through in AESTE Works. To sum up the work for this week, I did the cleanup and pushing to Github. The porting of FreeRTOS to the latest AEMB2 was not yet complete, but most of the relative issues had been identified and fixed.  The interrupt mechanism used during critical regions might not be useful and maybe the next person to take over from me can think of Read more

By erwen@aeste., ago

Debugging CPU

In this post I’ll explain how I debug the new core of AEMB, and the current bug that I’m facing. Debugging the CPU takes place using the demo program originally attached with AEMB. The waveform generated from the demo program running on the new CPU is compared with the waveform generated by AEMB. This way I try to ensure that the same instructions are executed in the same order with respect to each thread and that write backs are in Read more

By [email protected], ago

CPU Modifications

In the previous post I’ve explained how the threading model of the new AEMB. In this post I will explain all the changes to the old AEMB core that were necessary to accommodate a coarse grained model and sum up with an analysis of how the new threading model affects the performance. To begin with the major change was in the instruction address circuit. The registers holding the possible address for the next instruction were greatly altered. For a list Read more

By [email protected], ago