There is an interesting article in TC recently, about how it is now an excellent time to join startups. Just to note that AESTE is HIRING NOW. Quoting the article: Today, most interesting technology is built directly for end users and it is a crucial skill for an engineer to Read more…
This is a short introductory talk on Open Source Hardware given to a mixed crowd of both software and business types at a local FireStarter event organised by Hailer Communications.
An idea about hardware assisted synchronisation for the AEMB came about recently. The idea centered on the problem of how multiple threads would communicated between each other. The solution to this problem has always been synchronisation primitives. The AEMB already supports the atomic MSRSET/MSRCLR instructions, which can be used as Read more…
Seems like there are three important pieces of news to report: that the AEMB has made in-roads into China; that the AEMB has been implemented on Altera hardware; and that the AEMB is capable of booting uC/OS-II. According to the information provided at a Chinese media website, a key Chinese Read more…
While everyone seems to be quite focused on high-end virtualisation, there is also room for virtualisation solutions at the low-end. One way of approaching this problem is by the use of a thin layer of virtualisation at the nano-kernel level. Instead of just abstracting hardware away, it is also possible Read more…
Since the recent LLVM 2.7 release came with initial support for the Microblaze, it is now conceivable to add some features into the LLVM to enable power optimisation for the AEMB and other architectures. The reason that LLVM is chosen instead of GCC is purely subjective – a cleaner code Read more…
In order to streamline the new AEMB processor family, a new multi-threading model is being tested. In the new multi-threading model, each core will have at least the capability of running four threads either manually or automatically. For the AEMB1, the threads would need to be switched explicitly using special Read more…
The AEMB is designed with an FPGA target technology implementation. Since this is the case, it may be prudent to exploit certain FPGA capabilities that are not present on ASIC technologies. One such capability is the ability of an FPGA to pre-load the contents of block memories from an FPGA Read more…
Since increased concurrency seems like the way to go for computing, I am interested in increasing the concurrency of the AEMB from 2 to 4 hardware threads. This can be done through a dual-core set up. However, I plan to make my dual-core AEMB special by sharing resources between them Read more…
At present, all software is compiled using a custom GCC compiler backed by binutils and newlib. However, as the AEMB processor is sufficiently different from the original architecture, it may be time to start porting a new compiler to it. At the moment, the regular GCC compiler is used (with Read more…