As mentioned earlier, the idea of virtual peripherals is quite tempting on the AEMB core. The two independent hardware threads can be used to implement a single threaded application along with a second thread performing maintenance functions such as interrupt handling. It is therefore possible to implement some hardware peripherals in software.
The reason for this idea is the target market of the core. The AEMB is targeted at small and resource efficient FPGA implementations. It is often used in a complex System-on-Chip. It has been found that some of the peripheral I/O functionality connected to the core is actually larger than the core itself. Therefore, it maybe useful to investigate virtualising some of the peripherals.
One possible target implementation is an ethernet MAC. It is theoretically possible to implement a purely software MAC if high bit-rate is not required. Assuming that the AEMB runs at 100MHz, it is certainly possible to implement a 10-Mbps half-duplex ethernet MAC, which only needs to move data samples at the rate of 2.5MHz. Coupled with a few simple hardware blocks like a FIFO and GPIO, this should be possible.
Other possible virtualised peripherals would include common serial peripherals such as SPI/I2C masters. These are particularly possible as these transfers are all master controlled. A software implementation would be able to easily handle all the hand-shaking issues and not have to worry about random transfers initiated by the slave device.
Data can be passed between the main application thread and the virtual peripheral by shared memory buffers. A standard software FIFO could be used for this function. Special memory locations could also be reserved as configuration registers. This is actually a fairly exciting option.