In order to streamline the new AEMB processor family, a new multi-threading model is being tested. In the new multi-threading model, each core will have at least the capability of running four threads either manually or automatically. For the AEMB1, the threads would need to be switched explicitly using special software break instructions while for the AEMB4, the context switching will happen automagically and the AEMB2 will be somewhere in between the two.
As for the software, the AEMB1 will be focused for single-threaded applications. Therefore, it would only run a single-thread by default unless the switching is done explicitly. Once switched, it will continue to only run the new single-threaded code. It can do this hardware context switching for at least four threads. T0 will still be reserved for interrupt execution. So, a typical OS kernel would start T0 and run the c-runtime code before quickly switching over to T1 for the actual kernel code. It can possibly switch over to T2 or T3 for application code. When an interrupt happens, the core switches automatically back to T0 to execute the interrupt service routine before switching back to another thread.
At the other extreme, the AEMB4 will be focused for multi-threaded applications. It will run four-threads in hardware by default using interleaved multi-threading (IMT) techniques. Switching is done automatically for a true multi-threaded operation. A typical OS kernel would start on T0 and run the c-runtime code before activating T1-T3 for the application code. Each thread might be used to run different servers in a micro-kernel style OS. All interrupts will only be serviced on T0 without blocking the operations of the other threads.
This new threading model would hopefully find more real-world use by providing a versatile hardware platform for modern multi-threaded applications.
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