March 23, 2009

EDK63 Thread Independence

The EDK62 core introduced multi-threaded capabilities to the AEMB2 in the form of fine-grained multi-threading using a barrel processor. Essentially, it interleaves and alternates the instructions for the two threads on each clock cycle. However, the two threads are inter-locked, which means that one blocking thread will block the other Read more…

By Shawn, ago

EDK63 Cache Memory Block

Resource efficiency is always a goal of the AEMB2 design. In order to further reduce resource consumption and improve operating speed, some minor changes are being made in the next generation EDK63 core architecture. The first block to experience some changes is the cache memory block. Looking at the numbers Read more…

By Shawn, ago