Tag: verilog Page 2 of 4

The Final Task

This week is my last week of work as a part time engineer. I focused on the previous task that had been given, which is to develop a simple…

Analyze the Inferred HDL

This week, I have been working on the GPIO address and the C++ code. Previously, an assumption that had been made for the address of the GPIO registers,…

Automate Bitstream: Part 2

The task continues with more challenges, where I start to monitor the synthesis flow that had been set previously, starting from the generation of the HDL file to…

Automate Bitstream : Part 1

The Xilinx Synthesis and Implementation As I start to work on the synthesis and implementation flow, in order to generate the final bitstream that is being used to…

Project Continuation

After idling from Aeste for a month, I am back to Aeste again. The task now is to continue working on the previous intern project. Since I am…

The Final Week in AESTE

This week, the work goes to some optimization of the demosaic core, and some analysis to be done. The Removal of RAM Previously, I had mentioned in my…

Demosaic: Software vs Hardware

This week, the real comparison starts, to identify how much faster the demosaic core is, compared to software implementation. Software Implementation of Demosaic Previously, I had finished the…

Demosaic Core on Zedboard

Finally, after weeks of working on the demosaic core on software simulation, the real hardware implementation starts! The week went with the couple of frustrations on debugging the Xilinx…

Combination Demosaic Algorithms

Finally, this week I finished on the schematic of the whole demosaic core, described it in Verilog, and simulated it using the Icarus Verilog simulator. In the path…

Boundary Bilinear Interpolation

This week, things are getting clearer, and the work are getting better. I began to realize my previous mistake, that the image processing pipeline core might be driven…

Input & Output of Image Processing Pipeline Core

This week, I worked on the schematic of BRAM buffer and demosaic algorithm core. As I going deeper into the design, I found that I had lack of…

Pipelined Design for Demosaic Core

This week, I worked on the design of the circuitry for the demosaic IP core. On previous week, my supervisor and I has come to a conclusion of…

Correction on Design and Method

Propagation Delay This week, my supervisor had some discussion with me. The first problems was my timing circuits. Previously, I actually made the timing signals by altering the…

Synthesis of Verilog

This week, I continued to work on the timing signal generation for CCD sensor. It is also my first time to actually write a real Verilog code that…

Timing Signals for CCD

This week is pretty interesting, as I was working on the timing signals for the CCD. In order to perform demosaicing, my supervisor advised me to understand on…