Tag: verilog Page 2 of 3

Combination Demosaic Algorithms

Finally, this week I finished on the schematic of the whole demosaic core, described it in Verilog, and simulated it using the Icarus Verilog simulator. In the path…

Boundary Bilinear Interpolation

This week, things are getting clearer, and the work are getting better. I began to realize my previous mistake, that the image processing pipeline core might be driven…

Input & Output of Image Processing Pipeline Core

This week, I worked on the schematic of BRAM buffer and demosaic algorithm core. As I going deeper into the design, I found that I had lack of…

Pipelined Design for Demosaic Core

This week, I worked on the design of the circuitry for the demosaic IP core. On previous week, my supervisor and I has come to a conclusion of…

Correction on Design and Method

Propagation Delay This week, my supervisor had some discussion with me. The first problems was my timing circuits. Previously, I actually made the timing signals by altering the…

Synthesis of Verilog

This week, I continued to work on the timing signal generation for CCD sensor. It is also my first time to actually write a real Verilog code that…

Timing Signals for CCD

This week is pretty interesting, as I was working on the timing signals for the CCD. In order to perform demosaicing, my supervisor advised me to understand on…

Hardware Implementation of Demosaicing Algorithm

This week I was assigned to draw the schematic for the demosaicing algorithm. The algorithm is separated into two parts, which is bilinear interpolation in the boundary of…

Schematics from Verilog

This week, I had been assigned task on learning the schematics from Verilog. Schematic of Xilinx ISE I think this is a good approach in learning Verilog, because…

Introduction to Chip Design

I am officially in the midst of my internship now, and decided to try something new to me, which is chip design. I was given the tools of…

Verilog Integration

This week I started to integrate everything together starting from the generation of the C++ code by the user up to the creation of the final bit stream….

Data2mem Verification

Progressing from where I stopped last week, this week I had to finish everything up and make sure that everything works as it’s supposed to. Before I go…

FPGA Baby Steps

In this week, I started taking my first baby steps in the world of FPGA. I spent some times trying to get myself familiarized with the new tools…

Building Verilog Modules

Time flies by so fast, I can not believe that we almost approach the mid of the internship !! .. By writing this blog entry I can say…

Extracting I/Os Addresses

In this week I had to continue working in creating the Verilog top level module, to recap , for the past few weeks I have finished the instantiation…