Tag: verilog Page 1 of 4

Debouncing

Bouncing is the likelihood of metals to come into contact with each other, when the contact is opened or closed, producing unwanted multiple signals. Debouncing is the method…

Code Translation and JointJS

I work on generating Verilog version of source code based on user input which is coded in C++ this week. I study Verilog-mode and the way of this…

What Happiness Sounds Like…

My work on the passive buzzer had entered its 4th week. I did not like that 4 weeks means a month. When days become weeks, and weeks become…

Time is Never Enough

I thought taking few days off the week would leave me regretting for my work productivity as the time spent would not be enough. However, this week went…

Stop Counting The Effort. Make The Effort Actually Counts.

Unfortunately, this week did not go the way I planned. I worked extra days to cover a few leaves I plan to take later, thus with more time…

Progress Won’t Happen Without Struggle

Using one word to describe this week’s progress, that would be the word SLOW. Or more accurate, SLOWEST! The week however, just passed so fast. I was disappointed…

Buzzer : Active or Passive, It Must Sound

I started off this week by designing the code for a passive buzzer. It was quite a simple task as I only made a few changes compared to…

Effort is vital. But the key to make all the difference is knowing HOW and WHERE to put the effort!

I was having unfinished work from last week of not having the results I wanted from the test bench. The acknowledge signal of Wishbone does not behave as…

The Light That Lights My World

On Monday, I was almost done with the design code for my first module, a 7 colour auto flash LED. I chose this module to start with as…

37 sensors

This week had been exciting for me as now I have the Digilent Atlys Spartan 6 board to play with. Dr. Shawn taught me on USB over IP,…

Doing Things Does Not Mean Getting Things Done!

This week I started with having both SPI master and SPI slave verified for its functionality. Besides checking for the results of waveform graph manually, I also made…

Verification of Codes

I was not capable of verifying the codes that I modified because I had problems understanding how the output signal waveform should and should not be. I was…

Automated Test Bench

Test bench can be deterministic or self-checking. In deterministic test bench, the design’s output are simulated according to the design’s state and inputs specified in the test bench….

A Month of Internship

This week started off with me panicking when I could not find my saved files and codes. I asked Dr. Shawn about it and he fixed it rightaway…

Understanding Verilog Codes

Dr. Shawn would always remind me not to be consumed or lost in the programming language while learning Verilog as it describes the schematic in designing chips and…