Tag: verilog Page 1 of 4

Effort is vital. But the key to make all the difference is knowing HOW and WHERE to put the effort!

I was having unfinished work from last week of not having the results I wanted from the test bench. The acknowledge signal of Wishbone does not behave as…

The Light That Lights My World

On Monday, I was almost done with the design code for my first module, a 7 colour auto flash LED. I chose this module to start with as…

37 sensors

This week had been exciting for me as now I have the Digilent Atlys Spartan 6 board to play with. Dr. Shawn taught me on USB over IP,…

Doing Things Does Not Mean Getting Things Done!

This week I started with having both SPI master and SPI slave verified for its functionality. Besides checking for the results of waveform graph manually, I also made…

Verification of Codes

I was not capable of verifying the codes that I modified because I had problems understanding how the output signal waveform should and should not be. I was…

Automated Test Bench

Test bench can be deterministic or self-checking. In deterministic test bench, the design’s output are simulated according to the design’s state and inputs specified in the test bench….

A Month of Internship

This week started off with me panicking when I could not find my saved files and codes. I asked Dr. Shawn about it and he fixed it rightaway…

Understanding Verilog Codes

Dr. Shawn would always remind me not to be consumed or lost in the programming language while learning Verilog as it describes the schematic in designing chips and…

Communication Protocols

This week I continued to study further on the topic of Wishbone signals and also communication protocols. I tried creating testbenches for available codes that had been designed…

Second Week of Internship

This week I was assigned a few tasks by Dr. Shawn. The first one is to familiarize myself with tools such as Emacs and GTKwave. Emacs is a…

The Final Task

This week is my last week of work as a part time engineer. I focused on the previous task that had been given, which is to develop a simple…

Analyze the Inferred HDL

This week, I have been working on the GPIO address and the C++ code. Previously, an assumption that had been made for the address of the GPIO registers,…

Automate Bitstream: Part 2

The task continues with more challenges, where I start to monitor the synthesis flow that had been set previously, starting from the generation of the HDL file to…

Automate Bitstream : Part 1

The Xilinx Synthesis and Implementation As I start to work on the synthesis and implementation flow, in order to generate the final bitstream that is being used to…

Project Continuation

After idling from Aeste for a month, I am back to Aeste again. The task now is to continue working on the previous intern project. Since I am…