Tag: verilog Page 1 of 5

The Devil is in the details

This week, I started the week hoping to complete the Verilog code for the Analog Light Detector as success in implementing it would mean that I should be…

First hands on experience with Verilog

This blog post marks the end of my first week in Aeste.  In the past week, I’ve learning up Verilog, Git and the Wishbone protocol so that I…

The importance of Simplicity

This week, I learned to calculate the memory size of Kernel elf file and assign memory blocks accordingly. First, I need to generate an elf file from the…

The End of A Journey Does Not Matter, It Is the Journey That Matters, In the End

I started off this week by briefing a new intern that will be taking over my project as this is my last week of internship. I organized so…

Design’s Dependency

This week, I learned the importance of creating a program that is stable without relying on information from other files. This is important when it comes to designing…

When Good Enough Isn’t Good Enough

I continued to work on the large microphone only to find it was not working. It was weird as it has same characteristics as the small microphone and…

Module by Module

I carried on with the task of designing the modules in Verilog. I had chosen to work on the Infrared Transmitter and Infrared Receiver. This was quite exciting…

Flexibility in Naming

This week, I made a documentation about naming convention. I learned the importance of documentation and communication because it ensures a smooth workflow of project and it helps…

Half Done

At the beginning of this week, I realized I had only another month of internship to go which made me feel bad over the fact that I was…

Input Characteristics Determine Debounce Time

After much reading and some calculations, I learnt that theoretically the ideal bits of the LFSR counter in my design should result in the range of 300 µs…

WISHBONE

For this week, I work on instantiating the modules. Each signals’ name need to be the same as object’s name. For example, a signal named ‘ack_i’ should have…

One by One Till All Done

Modifying the debouncer design was how this week started and end for me. I used a counter for my previous design but this was not recommended by Dr….

Debouncing

Bouncing is the likelihood of metals to come into contact with each other, when the contact is opened or closed, producing unwanted multiple signals. Debouncing is the method…

Code Translation and JointJS

I work on generating Verilog version of source code based on user input which is coded in C++ this week. I study Verilog-mode and the way of this…

What Happiness Sounds Like…

My work on the passive buzzer had entered its 4th week. I did not like that 4 weeks means a month. When days become weeks, and weeks become…