List of tests for each IO core

I’ve implemented a list of tests for each device to test it’s behavior within specifications. Those tests are specific for each device. The set of tests is repeated for each possible value of the tested device parameters and each run with new parameter values has it’s expected output saved in Read more…

Automated Test Bench Algorithms

In the past month I’ve been experimenting with various approaches to create Automated Test Benches to my Verilog IO cores that are using Wishbone bus. The Automated part simply means that the test bench will verify the correctness of the received outputs and display a Pass or Fail message. This Read more…

Dear Verilator, Please Shut up!

Verilator does a great job notifying you about any possible source of error in your Verilog code. However, it’s not really the best sight getting a screen full of assorted warnings and errors whenever you compile a code with Verilator that was just working perfectly on Icarus. I don’t like Read more…

Verilator Explained

As part of my efforts to create “perfect” test benches I am to make sure the test benches work when compiled with different simulators. This approach is to expose language errors and any bugs in one of the simulators. Hence, I’ve tried to compile my test bench with Verilator and the process wasn’t Read more…

GPIO Automated Test Bench

In the previous post, Testing like a Pro, I explained some general guidelines to thoroughly verify the behavior of an RTL design. I’ve been working on the test bench for the GPIO over the past week. In this post I’ll explain it’s features and give a block diagram to two Read more…

Testing like a Pro

We are now using XCFE in Aeste, probably because it’s supposed to be a “light” desktop environment. However, I didn’t fancy it’s looks and absence of keyboard shortcuts similar to Ubuntu. Hence I took some time to make my desktop environment usable and setup some keyboard shortcuts. You can find Read more…