Tag: testbench

IO Cores Automated Test Benches

This post is a documentation of the final version of automated test benches created to verify our IO cores. The test benches have been created for the our…

Generic Automated Test Bench

The ultimate future goal is to create a generic Automated Test Bench that can be used with any of our IO cores. Of course the test vectors testing…

List of tests for each IO core

I’ve implemented a list of tests for each device to test it’s behavior within specifications. Those tests are specific for each device. The set of tests is repeated…

Automated Test Bench Algorithms

In the past month I’ve been experimenting with various approaches to create Automated Test Benches to my Verilog IO cores that are using Wishbone bus. The Automated part…

Dear Verilator, Please Shut up!

Verilator does a great job notifying you about any possible source of error in your Verilog code. However, it’s not really the best sight getting a screen full…

Generating 64-bit Hexadecial Numbers with Bash

In order to test my GPIO design whose width can vary from 1 to 64 bits I need to be able to generate random values to properly drive…

Verilator Explained

As part of my efforts to create “perfect” test benches I am to make sure the test benches work when compiled with different simulators. This approach is to expose…

GPIO Automated Test Bench

In the previous post, Testing like a Pro, I explained some general guidelines to thoroughly verify the behavior of an RTL design. I’ve been working on the test…

Testing like a Pro

We are now using XCFE in Aeste, probably because it’s supposed to be a “light” desktop environment. However, I didn’t fancy it’s looks and absence of keyboard shortcuts…