This week, I started the week hoping to complete the Verilog code for the Analog Light Detector as success in implementing it would mean that I should be able to complete all the remaining Keyes modules with minor adjustments for each. While I understood that the analog value is obtained by measuring the time for the capacitor to discharge, as different resistance values would result in a different slew rate, I have been trying all week to get an time value which can be represented by 16-bits (with the FPGA @ 100 Mhz) so that I can reliably test the circuit without a clock divider. I have not yet been successful so I’ve been reading up on the documentation for both the module and the FPGA to see if they might shed some light on my troubles.

In addition, I have refreshing my knowledge of C/C++ by reading up on structs, classes and pointers. This is so that I may begin implementing some of the C/C++ Drivers for the completed modules. I’ve been spending some time reading Structured Computer Organization by A.S. Tenenbaum to get a deeper understanding of how computers work and the role that the drivers play.

Looking forward to next week, I’m optimistic about starting work on the drivers, and hopefully, I will also be able to identify and understand my mistakes in the implementation of the Analog Light Detector.