This week, I learned to calculate the memory size of Kernel elf file and assign memory blocks accordingly. First, I need to generate an elf file from the C++ source code. Then, by using regex, I can extract the size of instruction memory and data memory from the elf file. Instruction memory is equivalent to ROM and data memory is RAM. For the company’s current choice of fpga (Xilinx Spartan6 LX9), each block of RAM is 18kbit configurable up to 2Kbyte block. Therefore, I can assign memory blocks according to the upper bound of memory size which is extracted from the elf file.

Then, I need to verify the Verilog source file which I spend a good number of weeks to generate. I need to synthesize the source file by using Xilinx. Credits will be giving to Alya who helped me not only on using Xilinx and also verifying the switch design I modified earlier by teaching me how to make use of test bench and check the timing graph. After some minor twists, the synthesis is successfully generated and the average time taken is 12 seconds and the amount of memory used is 400 kb.

Next week, I will make the program to do the synthesis by using Poco. Previous interns managed to do it by using boost filesystem, but the code is too complex and we are going to simplify it. The program is designed to trigger synthesis and send some information like the speed of CPU and size of memory used together with bit stream to the board.