This week, I learned the importance of creating a program that is stable without relying on information from other files. This is important when it comes to designing a robust algorithm. Initially, I made a program to extract information from generated Verilog file, so that the naming of pins from Json side matches with the naming on Verilog side. But this causes the program to be unstable as the timing of generating file could be simultaneous. Therefore, I redesign the program and make sure files do not rely on each other to generate information.

After finish up the naming convention, I redesign the switches and make sure those switches are compatible within a range of a single output to 16 outputs. In order words, the user can choose arbitrary number of i/o devices and the program will count the number of i/o devices and select a switch accordingly. This will avoid instantiating unnecessary signals and using the terminator.

Next, I will calculate the memory size of RAM and output an UCF header accordingly to locate the address of memory and the port of Fpga. Overall, a productive week well spent and I look forward to more exciting challenges in the future.