For this week, I work on instantiating the modules. Each signals’ name need to be the same as object’s name. For example, a signal named ‘ack_i’ should have an output like ‘B1_ack_i’ as ‘B1’ is the object name. This is achieved by using substring in an AUTO_TEMPLATE. Then I make sure the necessary information will be successfully captured by the computer. For now, I have each module instantiated and ready to be connected to the computer. To allow communication between CPU and IO devices, a switch and WISHBONE protocol are needed. A previous intern implemented the design by using more than one switch in several layers. But I plan to use just one switch and the switch is customizable depends on number of IO devices. This will reduces the complexity of code and also reduce the cost of production. My next challenge will be wiring up each modules to a switch and then to the computer. This will require knowledge of WISHBONE. I am excited and look forward to learning many new stuff.