Using one word to describe this week’s progress, that would be the word SLOW. Or more accurate, SLOWEST! The week however, just passed so fast. I was disappointed when I realized it was already end of the week and I have achieved nothing. Nothing – Not a thing, design code still not working, test bench failed, buzzer would not produce even the slightest sound, definitely.

I made a change to the clock divider module that was made before this for the previous buzzer. Dr. Shawn noted in my logbook where I wrote about clock divider, that it is encouraged to do a clock divider with the power of 2. That did not took long as it only required very small modifications. I continued with designing the counter for the current passive buzzer. I tested the buzzer with a simple program of making an ambulance siren just to observe the difference with different frequencies. Sure enough, the difference between the sounds coming from different frequencies were clearly heard from the buzzer.

Thus I proceed in doing a Wishbone interface to the design as well as writing the codes structure by structure with the schematic drawn by Dr. Shawn as a reference. It should be a simple task, involving designing Verilog codes using counters and reading the most significant bit (MSB) bit to send to the buzzer, yet to me it felt like it was such a complicated operation that I was not understanding thoroughly. I wrote the codes register by register and assigned output signals to its respective inputs. After designing, simulating and correcting errors again and again, I know I was not doing things right  as the test bench was just so, totally wrong. The results did not make any sense at all. There is no point in having no errors in a design, unless the design is right and is working as it should. All I know is that I must make it work soon, by hook or by crook.