Test bench can be deterministic or self-checking. In deterministic test bench, the design’s output are simulated according to the design’s state and inputs specified in the test bench. A designer would then have to validate that the outputs are working as it should. Meanwhile, in self-checking test bench, expected results are generated thus allowing the simulator to verify whether the actual outputs are tally to the expected outputs. This means that the designer does not have to go through the process of validating signals himself.
This week, I went on creating deterministic test bench to verify the code I edited which was really taking time whereas there was an automated test bench made by previous intern but I did not know how to run it. As soon as Dr. Shawn taught me about shell script and how to run them, I was able to verify my codes using the automated test bench available. I am quite lucky to get my hands on it as it was really helpful and convenient in which I can just specify my own parameters to change, it checks for every possible widths of GPIO and finally creates an output to acknowledge designer whether the design passed or failed. Dr. Shawn corrected my edited design since it came up with an error. I was happy that it finally worked even though it was such a small achievement considering the amount of time that I took.
From there, I could view the waveforms and validate apart from observing the difference when I changed some lines in the codes. I continued to do this for other communication protocols such as SPI and UART. Hopefully now I have sufficient knowledge and capability to start optimizing and writing codes for real.