This week which is my third, here at Aeste, was more about reading and understanding the current board. I started the week by redoing the Board Architecture that I worked on last week. At the time I did not fully understand what was asked, so I ended up doing it in a wrong way. The connection lines between components are shown in their respective data sheets, so all I needed to do was find the connections and figure out what kind of signal is being used. Dr. Shawn also pointed out that the I/O Port diagram does not look good (professional), so I generated an image of the board using Kicad and used that instead. The board looks much better now.


That was my next task. I need to know all the whys. In any PCB design, there are a lot of limitations such as physical, electrical, manufacturing and cost. Physical limitations, as the name suggests they are the restrictions caused by the physical properties of components. For instant putting a bulky component next to signal port might reduce the accessibility to that port. Electrical limitations are usually in form of noise, power loss and heat. Manufacturing could be an issue if the design requires a lot of resources and advance equipment, eventually, it would increase the cost of production.


This is one of the pins in the FPGA and it is interesting because it has a data sheet of its own. It suspends the FPGA, reducing the power consumption by about 40%. The good thing is no sacrifice has to be made since the mode of operation for each individual pin can be defined. In suspend mode pins can change state and as a result, the FPGA will be activated.