This week I started by trying to modify the FPGA code so that it would transfer in chunks of data rather than all in one go. Turns out a lot of the codes are not needed so Dr Shawn rewrote everything into less than 10 lines, this time using the Static SPI driver instead of Dynamic. The code now transmits the bitstream byte by byte.

Next I experimented with the usbcdc com port project in order to output a string to tera term. The demo project I based it on had a lot unnecessary code as the requirement was just to output a string. Initially when trying to use a char array as an argument to the function responsible for output, it will cause the output to print out corrupted data. The trick I found was to use a pointer to the char array instead as an argument, even though the original code just passed in the array without pointer as argument. The function takes in the type const void * which means it points to a memory that should not be modified. Also added was a code that gets the length automatically, this prints out the string perfectly.

Next was trying to integrate the usbcdc com port with the ethernet test project already created by a former intern. By checking the flow of the code, I managed to build an integrated code with both ethernet and usbcdc serial capabilities. The code managed to print out a string and also by using wireshark I was able to confirm that the network is also running at the same time.

After that I proceeded to try to integrate the FPGA project together with ethernet-usbcdc project. This time I found a problem in which the clock used for the ethernet clashes with that used in the FPGA. Only refclko4 can be routed to the clock input pins of both the ethernet and the FPGA, but they can’t be shared. I then tried to look into using the peripheral bus clocks to try to route the clock to the required pin to run the FPGA. There are some forums online that discuss trying to route pbclk to an external pin for testing, but there was no answer that I was looking for (their solution was to use pbclk as a reference for refclk, in which refclk will then be routed to an external pin for testing). The help documentation regarding pbclk also doesn’t list much aside from how to configure the frequencies in Harmony Configurator. Still unsure whether pbclk can be routed to an external pin for use, but from what I see it is used to drive peripherals such as SPI clock.