This week started with a mess. I started to confuse about what is my task all about, until my supervisor clarified me about it.
Add a SPI module
As I mentioned on my previous post, my task is to assign the SPI module into the FPGA, to form the communication bridge between the FPGA and the PIC. There are many ways to achieve this, and I had made many guesses before the implementation. The simplest and easiest way that I had thought, is to directly instantiate the SPI module in the top level module, and specify the FPGA pins in the UCF file.
Without modifying or adding any additional feature, I spent some time to understand on the generation of the top level module. By instantiating the SPI module together with the processor, the task could be completed. However, the problem comes with the addressing of the module.
How does the instantiated processor in the FPGA actually knows how to communicate with the instantiated SPI module? Well, after digging up the codes, I still could not find the answer yet, and I came up with another idea.
Alternative on Implementation of SPI module
Instead of cracking my head search for the addressing method of the processor to the SPI module, I looked up over the work that had been done. Apparently, Sumia had did a good job in the communication of the modules (gpio, lcd, etc.) with the processor. Using the existing code, adding a SPI module before any of the user module, could do the job. This would fix the address of the SPI module as one of the I/O device, which I could use it for SPI communication later.
Besides, this implementation actually uses one ID, where by default it would be ID zero. I found that this way of implementation actually saved me a lot of trouble, because the SPI module is treated just like an I/O device defined by user. Thus, all the other process after the top level module generation could be done smoothly.
The integration of work into the current project actually scared me in a moment, where I see the GPIO module simulation does not work. 😟 😟 😟 Using the advantage of Git, I revert back the changes, and I found that it was an original problem.
Next week, I will be focusing on the checking and make the synthesis of Verilog modules go smoothly. Hopefully, by the end of this week, I could also find out the addressing answer.