This week, I had been assigned task on learning the schematics from Verilog.
Schematic of Xilinx ISE
I think this is a good approach in learning Verilog, because I actually get to know how does the Verilog codes affect the circuits. At first, I was merely following the schematics that produced by the Xilinx ISE tools, I really felt that it is almost impossible for a human to draw a full schematic like that. However, after reading previous posts on the AEMB drawings, I realized that schematics drawing does not need to be as perfect as the Xilinx generated RTL schematics. The Xilinx ISE tool actually draw the RTL schematic in an optimized way, where they would cut off unnecessary components or minimize the circuit size. Thus, in order to draw a perfect circuit generated just like the Xilinx ISE, I drew a draft of the schematic using only Flip-flops, Multiplexers and logic circuits. From the draft of schematic, I would look for optimization circuitry, whether the circuit size could be reduced. Finally, I would refer back to the Xilinx ISE RTL schematic to verify the schematics.
For Verilog beginner like me, analyzing and observe the schematics from the Xilinx ISE RTL schematics is challenging. I actually get to wonder the red triangle that appears in the RTL schematics, and fortunately I able to find the answer from this Xilinx forum post. This symbol is widely used in the RTL schematics as it represent the bus or wires that connects to other pins. After drawing the schematics from some of the previous interns Verilog code, I become more familiarize with the Verilog coding.
Note: One important rule that should be kept in mind when drawing a schematic from the Verilog codes, is that it should only consists of Flip-flops, Multiplexers and Logic circuits.
Wishbone Bus Interface
Knowing that all the IP cores that would be used or designed should be Wishbone compliant, I spent some time reading on the Wishbone bus interface. I found that this link is useful to know about Wishbone and how it actually got applied in real application.