I am officially in the midst of my internship now, and decided to try something new to me, which is chip design. I was given the tools of Atyls Spartan 6 FPGA development board for the development of chip design.
The Xilinx ISE tool
There are many documentations provided by Xilinx, it is just matter of time to finish all of them, or to choose the important ones and focus on them. I found that this ISE in-depth tutorial is very useful, especially for beginner that did not use any of the Xilinx tools before. It provides step by step tutorial for learning how to use the ISE tool.
Learning on Verilog
The chip design is written in Verilog language, which is a popular description language, used to replace the usage of schematics in drawing circuits. Verilog is interesting but also can be found difficult to understand sometimes. In AESTE, there are so many posts about Verilog, which contributed by previous interns, one of the best reference I found was from my senior Mostafa’s post. As initially I was quite confused on the usage of Xilinx tools to write Verilog and simulation, or to use the Icarus Verilog simulator and GTK wave viewer.
However, I found that the Xilinx ISE is very effective in determine the final schematics that could be generated from the Verilog codes. This is extremely critical in chip design as a chip designer would always need to verify his or her final design in schematics, instead of just writing Verilog and verfiy the output. Sometimes, the design may just be unpractical, because a complicated Verilog code could result in a large circuit that would need more optimization. Meanwhile, the Icarus simulator and GTK wave viewer is fast and easy to be used.
Continue from previous week work, I finally finished the memory map of the simulator, which turn outs that the simulator instruction would start from address 0000 0000, and suppose to finish at 0000 7FFF, which is exactly 64 kilobyte. I had an argument with Sumia on this because I was confused with the calculation. At last, I understand that each address would only occupy 2 bytes, which 4 addresses would occupy for 8 bytes, which is exactly 32 bits. Therefore, the calculation for total space that would occupy for instructions would be 64 kilobyte, which is
65536 / 2 = 32678 (hexa : 8000)
Also, one thing that I wanted to highlight one of the founding I did, which is on the RAM address of 0000 0000. RISC-V Angel would hard code this specific address to the total memory size of the RAM. This makes me wonder somehow that is all the processor actually save their memory size number in their first address of RAM.