The goal of this month is to get everything in the project working starting with the code the user is going to enter until the final bit stream that can be downloaded to the FPGA. This week has been quite productive.

First of all the SOC is complete. I have tested various modular switches differing in the number of devices each accommodates. I have tested switches that can accommodate numbers of devices starting from 2 devices all the way to 64 devices. The difference is that the more devices the switch accommodates the bigger the multiplexers and decoders inferred by the switch. I used the synthesis results to find the optimum choice in terms of speed and area. Since all my switches don’t contain any synchronous device they were all equal in the speed factor. To begin with I made a graph of number of devices VS. LUTs consumed for each switch. Apart from the 2 devices switch case,  this graph wasn’t of much help in determining the optimum choice as the relation was an exponential one. Thus, I used the number of LUTs per device for each switch as a decisive criteria. I found that for the Spartan 6 FPGAs, building my switches to accommodate 4,8 or 16 devices are the optimum choice. Increasing more devices  uses more LUTs per device. Since our first prototype won’t accommodate more than 16 devices I decided to use the 16 device switch.

As for the accelerator switch, I decided to use the 8 device switch as our prototype can’t accommodate more than 8 accelerators.

Now that all the design is ready I created a sample top module along with a guide on how to create this top module based on the users preferences. After the top module is ready, it’ll run through Emacs Verilog-mode which will automatically create all ports declarations and module instantiations.

Second, I created a script that can synthesize the HDL design and Implement it for FPGA using Xilinx tools from the command line. Xilinx provides a very comprehensive user guide on using its tools from the command line. The only tool not included in this guide is the Xilinx Synthesis Tool XST which has its own user guide. I found it helpful to obtain the commands used by the ISE during the process, analyze them and choose the suitable options for my implementation then arrange them all properly in one script file ending with the Data2mem for initializing the block ram. In the process I created quick guides for the command line options for future reference.

To sum up, the SOC is ready for testing with a script for running Xilinx tools and a guide on how to create the top module.