This week although wasn’t that productive but I still manage to start working a little on the following new stages that are the 4th stage-Memory Access and the final stage-WriteBack. The first 2 day of the week I continue on code checking before further implement the following stages. Carry bit were checked for any arithmetic and shifting instructions that involved carry flag -MSR[29].

In Memory Access stage, I need to use appropriate getMem() and setMem() to read and write memory for both load and store instructions. The “appropriate” means here is to used suitable data type when calling the getMem() function and also setMem() function because there are 3 different data type used for both load and store instructions that is byte (8 bit), half word (16 bit) and word (32 bit). For load instruction, memory content is load from the memory location that results from adding the contents of registers rA and rB that have been execute in Execute stage. The data is placed in the least significant byte of register rD. Whereas for store instruction is to store content of register into memory location that result from the adding of content execute in Execute stage. Besides implementing the load and store instructions in memory access stage, branching also need to be taken care of especially branching instructions with linked and delay purpose. If linking is performed, the current value of PC will be stored in rD in WriteBack stage whereas for instruction with delay slot, I need to implement the function so that the instruction following the branch (i.e. in the branch delay slot) is allowed to complete execution before executing the target instruction. If the branching without delay slot it simply means the instruction is to be executed after the branch is the target instruction. For branching cases, setRPC() function is used to change the program counter  to a new location. In the last pipeline stage-WriteBack, all data need to be save into register file and thus setReg() function is used. The data can be come from Execute stage result, Memory access (load instruction) or Branch (with linked).

Currently I am figuring out how to implement so that carry bit is also being taken into account when arithmetic instruction without carry bit and keeping the carry bit is executed. This can be said as a  precaution step as there might be chances where carry bit is involved in pure arithmetic operation. I have informed by my supervisor that in order to implement this, i need to set the carry bit manually using setMSR() function where carry bit is set to 1 if both most significant bit of operand A and operand B is 1 for addition whereas for subtraction, the carry bit means “borrow”. Supervisor leave this part for me to figure out myself and I am thinking maybe i can set the carry bit if most significant bit of operand A is 0 whereas operand B is 1. Not 100% confirm but will try and error on it again.