Several months have passed since development on the next generation AEMB core started. During this time, there has been some experimentation on features and architecture, as well as design considerations made, to improve the performance of the core. Some improvements were made to accommodate the ability to execute dual-threads in hardware, while others were made to speed up the pipeline. The major changes are listed below:

  • Upgraded compatibility of core to EDK 6.2 compatible.
  • Integrated on-chip instruction cache memory.
  • Added atomic MSRSET/MSRCLR test-and-set/clear instructions.
  • Added software controllable tag signals to each Wishbone bus.
  • Completed support for an accelerator Wishbone bus.
  • Added a C/C++ software library for compatibility.
  • Accurate and well defined interrupt support.

Some issues that are in the pipeline are:

  • Code compatibility across vendor technologies.
  • Hardware resource optimisation.
  • Improved software support.

Since the AEMB is now EDK 6.2 compatible, hardware development will be paused. Only bug fixes and performance optimisations will be made in the near future. Focus will now be placed on software support. The AEMB software libraries need to be created and updated for general use. An example application and possible embedded OS integration is also planned.

Although the latest core designs are available in the CVS repository but they are not suitable for production use at this time. They are available for some initial testing. Post place and route performance seems promising to date. It achieves 100MHz performance on a Spartan3A/CycloneIII and 210MHz performance on a Virtex5 using default synthesis and place and route parameters.

Please feel free to send feedback if you test out the core.