As I have mentioned in the previous post, this and the coming posts would describe ASH1 architecture and special features.
Below is the block diagram of ASH1.
It consists of a data stack, a control unit, a program counter, an arithmetic/ logic unit (ALU), a cyclic redundancy checksum (CRC) unit, an input port, two output ports, a wishbone interface unit, a register file, two FIFO buffers, and three flag registers. These components are interconnected among each other via two buses; data bus (dbus) and address bus (abus).
ASH1 instructions are 14-bit wide with one cycle per instruction (except for one type of CRC instruction), while its operands are 8-bit wide. The wishbone bus along with a set of interrupt signals enable ASH1 to communicate with upper controllers (e.g. Master CPU).
The instruction set is made up of 17 instructions optimized for I/O operations in terms of packet fields building and signaling.