Time was passing really fast and this was the eighth week of internship. In this week I was working on a Wishbone RAM.

To start off, I had to understand the mechanism of a dual port RAM. The dual port RAM fundamentally consisted of an instruction port (read only) and a read/write port. An address of 0x00000000 would be passed into the instruction port whereas 0x80000000 would be passed into the read/write port. However, they should have the same data and the data would be stored at the least significant bit (LSB) of the address.

In addition, I would have to create a Wishbone RAM. The Wishbone RAM acted as a wrapper and four dual port RAMs should be instantiated within this wrapper, as a total of 32-bit data would be passed into the Wishbone RAM. On the other hand, the depth, as well as the address line, would be determined based on the file size generated. To instantiate four dual port RAMs at one time, I used an AUTO_TEMPLATE as shown below.

/* dpsram AUTO_TEMPLATE(
.dat_o([email protected]_dat_o[WORD_LENGTH-1:0]),
.xdat_o([email protected]_xdat_o[WORD_LENGTH-1:0]),
.adr_i(adr_i), .dat_i(dat_i[@”(+ (* 8 @) 7)”:@”(* 8 @)”]), .wre_i(wr_en),
.xadr_i(xadr_i), .xdat_i(dat_i[@”(+ (* 8 @) 7)”:@”(* 8 @)”]), .xwre_i(1’b0),
.clk_i(clk_i), .ena_i(sel_i[@]),
) ;

Furthermore, I had to design the wiring for signals within the Wishbone RAM so that it could give accurate results. The signals were required to be wired directly from the Master to minimise the processing time.

Moreover, two registers were created to indicate acknowledgement signals of instruction and read/write ports respectively. The two registers would be asserted when there was an input of strobe and negated after one clock cycle.

As a result, a timing diagram for the Wishbone RAM could be obtained. The following timing diagram showed a SINGLE READ/WRITE cycle.

It was also possible to have two inputs of addresses and data could be read from the two addresses at a later time. This process was demonstrated in the timing diagram below.

In conclusion, the Wishbone RAM was completed and I would start to work on generating a single top level design Verilog file next week.

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