FPGA families overview

Field Programmable Gate Array (FPGA) is a type of hardware/logic programmable integrated circuit. It’s flexibility, speed and the increasing number of IP cores make it into a popular solution in embedded system.

The selection of the FPGA core is important when designing a FPGA system. FPGA vendors divide their products into few groups. Each group targets different application such as high performance, mid-range, low cost and low power application. Furthermore, each product group can divide into few families. Every family have different features to support the target applications.

The parameters listed below are important when selecting a FPGA core for a system.,

- Logic Cells/Elements
- Block RAM
- Hard IP block (eg. memory controller and DSP block)
- I/O Pin
- I/O logic level
- Configuration method
- Power consumption
- Cost
- Avaibility
- Supported tools

Since the architecture of logic cells, block ram and DSP block architecture is different between families. Therefore the comparison are not straight forward. The synthesis tool and the logic block architecture may vary the number of logic elements that used by a design.

Most FPGA vendors don’t specify the total power consumption of each devices since it depends on the system design, frequency, and core voltage that used by the system. However, FPGA vendors offer power calculator/estimator that can roughly calculate the power consumption.

Price may vary with different distributer. It is difficult to conclude that which family provides the higher performance-price ratio. If the price is important, then try to contact local distributer to quote the price.

Some of the FPGA vendors and their families are listed below. All parameters are based on the maximum value from each family.

Xilinx
The company offers three SRAM based FPGA families that cover high performance, mid-range and low cost application. Xilinx also offers some special grade FPGAs like space grade, defence grade and automotive grade FPGA. Some of the family are listed here.

  • Virtex – Xilinx’s high performance FPGA. It offers highest logic cells capacity that enabled by stacked silicon interconnect (SSI). The family targets for ASIC prototyping and high performance communication systems.
  • Spartan – Low cost FPGA. The family targets for high volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications . Xilinx announce the Spartan 6 series is the end of the series and has been succeed by two families – Kintex and Artix.
  • Kintex – Mid-range mixed signal FPGA. Optimized for highest performance-price ratio. The family targets for high performance signal processing, long term wireless network and 3D flat panel display.
  • Artix – Low cost mixed signal FPGA. Optimized for lowest cost and power with small form factor packaging for the highest volume applications. The family targets for medical devices, handheld devices and automation applications.
  • Feature Spartan 6 Artix 7 Kintex 7 Virtex 7
    Type SRAM based SRAM based SRAM based SRAM based
    Logic Cells 147K 360K 478K 1,955K
    Block RAM 4.8Mbit 19Mbit 34Mbit 68Mbit
    Configurable ADC - 17 channels 16 channels -
    DSP slices 180 1,040 1,920 3,600
    IO Pins 576 600 500 1,200
    PCI-e x1 Gen1, Endpoint only x4 Gen2, Root & Endpoint x8 Gen2, Root & Endpoint x8 Gen3, Root & Endpoint
    Configuration JTAG, Master SPI, Master BPI, Master/Slave Serial, Master/Slave SelectMAP JTAG, Master SPI, Master BPI, Master/Slave Serial, Master/Slave SelectMAP JTAG, Master SPI, Master BPI, Master/Slave Serial, Master/Slave SelectMAP JTAG, Master SPI, Master BPI, Master/Slave Serial, Master/Slave SelectMAP
    Configuration bits (x) 3Mbit<x<33Mbit haven’t release 23Mbit<x<143Mbit 107Mbit<x<427Mbit

    To synthesis a design for Xilinx’s FPGA, Xilinx offers a software pack called ISE design suite to simplify the development cycle. A free edition – ISE webpack is also available but only support limited device.

    Altera
    Similar to Xilinx, Altera offers three FPGA groups that cover high performance, mid-range and low cost application. They also supports wide temperature range for commercial, industrial, extended industrial, automotive, and military application. Three major family are listed below.

  • Stratix – Altera’s high performance FPGA family. It targets for high performance communication systems and ASIC prototyping.
  • Arria – The family targets for cost sensitive applications that require high performance computation functionality, such as digital signal processing (DSP), wireless, wireline and video end markets. Latest series also intergrates an Dual-core ARM Cortex-A9 in the same die.
  • Cyclone – The family targets for high-volume applications at the lowest cost and lowest power (compares to Stratix and Arria), such application are industrial automation, wireless, wireline, consumers and automotive.
  • Feature Cyclone V Arria V Stratix V
    Type SRAM based SRAM based SRAM based
    Logic Cells 301K 504.14K 952K
    Block RAM 11.6Mbit 24.14Mbit 52Mbit
    DSP Block 342 1,156 704
    Users IO 488 704 840
    PCI-e x4 Gen2 Root and Endpoint x8 Gen2 Root and Endpoint x8 Gen3 Root and Endpoint
    Configuration JTAG, Active Serial, Passive Serial, Fast Passive Parallel, PCIe JTAG, Active Serial, Passive Serial, Fast Passive Parallel, PCIe, Internal Hard Processor System JTAG, Active Serial, Passive Serial, Fast Passive Parallel, PCIe, Partial Reconfiguration
    Configuration bits (x) 20Mbit<x<190Mbit (some of the devices haven’t release) 66Mbit<x<177Mbit 89Mbit<x<370Mbit

    Altera offers a software development suite called Quartus II to simplify the development cycle. A free web edition is available but only support limited device.

    Lattice Semiconductor
    Lattice also focuses on SRAM based FPGA. The company offers three major FPGA groups, they are high-value, high performance and non-volatile FPGA. Lattice also offer a very low power FPGA which is known as mobileFPGA, a series of FPGA that acquires from SiliconBlue.

  • SC – Lattice’s high performance FPGA. It delivers best in class solutions for high throughput standards like Ethernet, PCI Express, SPI4.2 and high speed memory controllers.
  • ECP – High-value FPGA. It’s target applications are wireline, wireless communication and video processing.
  • XP – SRAM based FPGA with internal flash memory. The architecture simplify the board level design since no external configuration flash memory is needed.
  • iCE – This family is known as mobileFPGA. It focuses on the applications that require low power, less space and less bill of materials, such as smartphones and tablets.
  • Feature iCE40 XP2 ECP4 SC
    Type SRAM based (with internal non-volatile memory) SRAM based (with internal non-volatile memory) SRAM based SRAM based
    Logic Cells 16K 40K 241K 115.2K
    Block RAM 384Kbit 885Kbit 10.62Mbit 7.8Mbit
    DSP Block - 8 576 -
    Users IO 222 540 512 942
    Configuration Master/Slave SPI (ISP or Socket Adapter) JTAG, Master/Slave SPI JTAG, Master/Slave SPI, I2C, Parallel (8bit or 16bit bus) JTAG, Master SPI, Master/Slave SPI, Master/Slave Parallel, MPI -8 -16 -32
    Configuration bits (x) 120Kbit<x<2114Kbit 1.27Mbit<x<8.03Mbit 10.7Mbit<x<54.5Mbit< 4.6Mbit<x<35.8Mbit

    Lattice also offers software design suite called Lattice Diamond. A free license is available but with limited device support.

    Microsemi (formally Actel)
    MicroSemi focuses on Flash based and one time programmable FPGA. The company splits their products into four major groups, they are low power, mixed signal, radiation tolerant and Anti-Fuse FPGA. Each group can further divides into few families. Few of the families are listed below.

  • IGLOO – Low power FPGA with integrated flash memory. It targets for portable, display and human machine interface application.
  • SmartFusion – Mixed signal FPGA. Come with hard 32-bit ARM Cortex-M3 microcontroller core, programmable analog with analog-to-digital converter (ADC), voltage/current/temperature monitors, digital-to-analog converter (DAC), comparators, and analog compute engine (ACE).
  • RT ProASIC – Re-programmable radiation tolerant FPGA. It targets for military and aerospace appications.
  • Axcelerator – High speed Anti-Fuse FPGA. It targets for consumer, industrial, medical, military and aerospace applications.
  • Feature IGLOO SmartFusion RT ProASIC3 Axcelerator
    Type Flash Based Flash Based Flash Based One Time Programmable
    Logic Cells 75,264 11,520 75,264 10,752(Register) 21,504(Combinatorial)
    Block RAM 504Kbit 108Kbit + 64MByte from ARM 444.9Kbit 294.9Kbit
    Users IO 620 128 620 684
    FlashROM bit 1024 512KByte (using ARM’s flash memory) 1000 - (Anti-Fuse)
    Programming JTAG JTAG JTAG JTAG

    MicroSemi also offers a software called Libero that integrates all the nesessary tools for FPGA. Free editions are available, but not all functions are supported. Although the numbers of logic cells are lesser than previous companies. However, the attracting points of these families are the power consumption and non-volatile logic cells.

    Some families from four major FPGA vendors are listed above. The numbers from each table are for reference only. Please refer to the datasheet for the exact parameters.

    Here are some suggestions for FPGA selection:

  • Using the vendor specific synthesis tool to synthesize the design. This should get the number of logic elements that used by the family.
  • Using the vendor specific power estimator roughly calculate the power consumption. Is that over the maximum capability of power supply?
  • Choosing the FPGA that meets your peripherals’ I/O count and logic level. More I/Os mean more power consumption and cost.
  • Choosing the FPGA that meets your design’s RAM size.
  • SRAM based, Flash based or Anti-Fuse FPGA. Difference type will result in different board level design/layout.
  • Contact your local distributer for price quotation if the cost is sensitive.
  • Check if any supporting design tools are available for the FPGA.
  • When the family/device will become obsolescence. Find the latest product may prolong the life cycle of end product.
  • Other constrains like form factor, temperature and radiation tolerant are important for some applications. Consider them if they are needed.

    FIRST LEGO League 2012

    As in previous years, I participated in the Malaysia Open Championship of FLL as a judge. This year, I was promoted to head judge for the project judging and had to manage 8 judges judging 48 teams for the competition. As I have done several rounds of judging before, I was looking forward to enjoying the show this year.

    The presentation judging proceeded without a hitch. All the teams proceeded with their presentations on time and the judges were fully cooperative. In the end, we came up with the list of winners with little argument. Some other judging teams spent several hours deliberating over their winners.

    I tried a different system of judging this time around, which I had learned from participating in the F1 in Schools World Finals last year. The system was designed to adjust for skews in judging and to make it easier for judges to come to a decision on the winners.

    All in all it was pretty smooth.

    I was also involved as a judge for the performance category of the competition – the most exciting part. I judged the final round of competitions on the final day. It was either do-or-die for some of the teams competing for titles.

    This part of the competition never fails to disappoint. It is always full of energy, with teams fighting to drown out each other when cheering for their team mates. The missions this year were the most difficult I had seen for the last few years. I’m surprised that some of the teams actually did as well as they did.

    Actually, I should rephrase that last sentence. These students never fail to surprise me with their creativity and innovative ideas.

    I would seriously like to get more involved in FLL in the future. I think that it might be a good opportunity for AESTE to sponsor and mentor a team to win the competition in the future. We might also get involved in terms of providing some software for the competition.

    Some things to consider.

    Taylor’s Engineering Fair 2011

    I was invited to be a guest judge for the Engineering Fair 2011 at Taylor’s University today. The fair is a showcase for the first year and third year projects of the various engineering students at Taylor’s. After finishing with the judging work, I went around to have a look at the projects personally.

    It was a smart thing for them to coincide the Engineering Fair with the Open Day this weekend. As a result, parents and students who are shopping around for a university would get the opportunity to look at some of the student projects on display.

    Some of the projects were quite interesting and the students’ enthusiasm for their project was quite evident. Some of the students caught me and I spent some time giving them advice on how to best exploit their time in engineering school. Too bad that they were a bunch of chemical engineering students.

    Generally, I get the impression that the students who go to the university seem to be pretty decent. Some of them are actually downright impressive in terms of their personality and character. I would peg them squarely as achievers based on my limited dealing with them.

    Unfortunately, I’d learned that the number of electronics engineering students that they have is a rather small one as it is the smallest engineering programme that they have. Thankfully, I have also heard that their numbers are on the increase and this is good news for me as I hope to be able to increase the pool of electronics engineers in Malaysia as a whole.

    I do hope to establish more links between AESTE and various local engineering schools. I have close research and student links with two GLC universities and I’m hoping to diversify my pool of universities to include private and public universities next year.

    This whole fair actually reminded me of the days when I was the EDX (Engineering Design Exhibition) director at my old alma-mater. It used to be a massive affair for us as we would invite high school students from across the state to come and visit the university.

    Those were the carefree days of fun.

    Physical Programming #3

    Yesterday, I went to Universiti Kebangsaan Malaysia (UKM) in Bangi, to deliver a talk on physical programming. This is the third such talk that I have been delivering in various local universities, with the previous two at Universiti Teknologi PETRONAS and Multimedia University.

    However, UKM is of note because of the reception that I received there. It was the biggest crowd of students that I had ever addressed, with about 50 students attending and filling up half the lecture room. Also, I was treated to a simple working lunch there with some of the staff.

    The students themselves seemed interested in the talk as they were quite attentively listening, and also asking relevant questions and providing suitable answers. I actually took it as an opportunity to survey most of the students to see if there are any potential ones for hiring.

    I have two reasons for delivering this talk – one is to pitch ourselves as a career destination of choice; and to expound the concept of physical programming, which is not new but is an enlightening thing. I do hope that the students heed my advice and to always think before they code.

    As an engineering startup, it is vital for us to build strong links with local universities. This is critical to ensure that we will always have a supply of fresh graduates and also to ensure that we can collaborate on cutting edge research work.

    I’d happily go back to UKM regularly.

    Visual Diff

    http://www.evilmadscientist.com/article.php/visdiff

    As an open source hardware shop, we have to contend with some serious limitations when it comes to source control tools.

    However, this person has come up with a way to do visual diffs of circuit schematics and PCBs using existing tools.

    All the we need to do is to adapt it to our standard processes.

    Yeay!