Seems like there are three important pieces of news to report: that the AEMB has made in-roads into China; that the AEMB has been implemented on Altera hardware; and that the AEMB is capable of booting uC/OS-II. According to the information provided at a Chinese media website, a key Chinese university (Shandong University of Science and Technology) has successfully implemented an SoC system using the AEMB on an Altera platform and boots uC/OS-II.

They published a paper on this earlier this year. The details are mostly in Chinese but some information can be gleaned from the diagrams and references. This is a verification paper on the capabilities of an AEMB SoC to boot uC/OS-II on an Altera platform. The SoC has a number of peripherals and uses a Wishbone bus.

MicroC/OS-II (commonly termed µC/OS-II or uC/OS-II), is a low-cost priority-based pre-emptive real time multitasking operating system kernel for microprocessors, written mainly in the C programming language. It is mainly intended for use in embedded systems.

The AEMB has previously been shown to boot Linux and now it is shown to boot uC/OS-II. There should be no reason why it cannot boot other operating systems as well. According to the paper, they had to put in some minor effort to port uC/OS-II to the AEMB. This is in line with other reports of easily booting Linux on it.

However, to my knowledge, the AEMB has never been shown to work on the Altera platform. While care has been taken during the design process to cater to all popular hardware platforms, by ensuring that the code can be understood and synthesised by each vendor’s tools, it has never been tested on working Altera hardware until now.

So, the things to learn from this paper:

1. AEMB has now found a home in a key Chinese university. They may be developing further applications on it.
2. AEMB platforms can run on a Altera hardware platform. This broadens the possible hardware implementations.
3. AEMB is capable of running uC/OS-II – a popular RTOS. This ensures that the AEMB is capable of real-time applications.

Several months have passed since development on the next generation AEMB core started. During this time, there has been some experimentation on features and architecture, as well as design considerations made, to improve the performance of the core. Some improvements were made to accommodate the ability to execute dual-threads in hardware, while others were made to speed up the pipeline. The major changes are listed below:

• Upgraded compatibility of core to EDK 6.2 compatible.
• Integrated on-chip instruction cache memory.
• Added atomic MSRSET/MSRCLR test-and-set/clear instructions.
• Added software controllable tag signals to each Wishbone bus.
• Completed support for an accelerator Wishbone bus.
• Added a C/C++ software library for compatibility.
• Accurate and well defined interrupt support.

Some issues that are in the pipeline are:

• Code compatibility across vendor technologies.
• Hardware resource optimisation.
• Improved software support.

Since the AEMB is now EDK 6.2 compatible, hardware development will be paused. Only bug fixes and performance optimisations will be made in the near future. Focus will now be placed on software support. The AEMB software libraries need to be created and updated for general use. An example application and possible embedded OS integration is also planned.

Although the latest core designs are available in the CVS repository but they are not suitable for production use at this time. They are available for some initial testing. Post place and route performance seems promising to date. It achieves 100MHz performance on a Spartan3A/CycloneIII and 210MHz performance on a Virtex5 using default synthesis and place and route parameters.

Please feel free to send feedback if you test out the core.

A new AEMB core is in the works. It will feature a radical departure from the present compatible architecture, while maintaining software compatibility. It has twice the clock rate of the present core and can execute two hardware threads. There are also other improvements made to the core. Initial results have been extremely promising, delivering a doubling in code performance.

After the development of the AEMB 7.11 got wrapped up, there were many ideas floating around, on things to improve. These ideas are mainly driven by user feedback. So, the plan is to build a next generation AEMB, which will feature a departure from the traditional architecture, while maintaining full software compatibility.

Chiefly, the improvements to look out for in the new core are:

• Increased Clock Speeds
  The new AEMB will feature a 5-stage integer pipeline. The shortening of each individual stage results in the doubling of the effective clock rate, over the present clock rate. Many of the issues that were slowing it down previously, have been resolved. So, you can expect the new core to run at twice the clock speed of the present AEMB.
• Fine Grain Multi Threading
  Another radical departure for the core is the implementation of FGMT, which is capable of executing 2 hardware threads. This will reduce latency and increase instruction throughput. Instructions are no longer wasted when dealing with code bottlenecks and slow devices, which makes is suitable for high performance embedded applications

Besides these two main changes, there are many other improvements being done on the architecture. As a result of all the improvements, code performance can be expected to increase by 2.5 times. There are many potential exciting applications that can be built for this new core. Hopefully, this will keep the AEMB useful and exciting for various embedded projects.

An initial development version is now available in CVS. It is potentially buggy and the architecture has not been finalised. It should only be used for evaluating the potential of the new core. It is not yet recommended for production use until further testing is complete.